M ar c h 2 00 6
S am ur ai - 6M / M X
6 P or t 1 0 /1 0 0 M bi t / s S i ng l e C h i p E t h e r n e t S w i tc h
C o n t r ol l e r ( A D M 6 9 9 6 M X - G r e en P ac k a g e
Version)
A D M 69 9 6 M / M X , V e r s i o n A D
D a ta S h e e t
R e v is i o n 1 . 4
Communication Solutions
Edition 2006-03-24
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ADM6996M/MX, 6 Port 10/100 Mbit/s Single Chip Ethernet Switch Controller (ADM6996MX - Green
Package Version)
Revision History: 2006-03-24, Revision 1.4
Previous Version: Rev. 1.23
Page/Date
Subjects (major changes since last revision)
Page 15
Rev. 1.2: Modify analog pins number (RXP4-0, RXN4-0, TXP4-0 and TXN4-0)
Page 81-82 Rev. 1.21: Rearrange 0EH and 0FH registers map
Page 22
Rev. 1.22: Modify LNKFP5 pin description/1B, Link Failed
2005-07-04 Changed to the new Infineon format
2005-07-04 Rev. 1.22 changed to Rev. 1.23
2005-08-23 Rev 1.3: Update in content
2005-11-01 Revision 1.3 changed to Revision 1.31
Minor change. Included Green package information
2006-03-04 Revision 1.31 changed to Revision 1.4
Modify 3.1.10 Bandwidth Control and add Table 4 Bandwidth Control Timer Select
Modify 3.1.15.3 and Figure 5 Configure Samurai QoS Function
Correct Figure 10 Full duplex MAC to MAC MII Connection
Add 29H[10:9] register for BCTS and 29H[8] register for BPM
Add thermal resistance information
Trademarks
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®,
INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®,
QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™,
VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® is a registered trademark of Microsoft
Corporation, Linux® of Linus Torvalds, Visio® of Visio Corporation, and FrameMaker® of Adobe Systems
Incorporated.
Template: template_A4_3.0.fm / 3 / 2005-01-17
Samurai-6M/MX
ADM6996M/MX
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1
1.1
1.2
1.3
1.4
1.5
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Samurai-6M/6MX (ADM6996M/MX) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
11
12
12
2
2.1
2.2
2.3
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
14
3
Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2
Buffers and Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3
Full Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4
Half Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5
Back-Off Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.6
Inter-Packet Gap (IPG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.7
Trunking Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.8
Illegal Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.9
Broadcast Storm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.10
Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.11
Smart Discard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.12
LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.12.1
Single Color LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.12.2
Dual Color LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.12.3
Circuit for Single LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.12.4
Circuit for Dual LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.13
Packet Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.13.1
Span Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.13.2
Management Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.13.3
Cross_VLAN Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14
Tagged VLAN or Port VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.1
VLAN Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.2
Port VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.3
Tagged VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.4
VID for Comparison and Carried through Samurai-6M/6MX (ADM6996M/MX) . . . . . . . . . . . . .
3.1.14.5
Admit Only VLAN-Tagged Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.6
VID Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.7
FID and VLAN Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.8
Ingress Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.9
VLAN Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.10
TXTAG Carried through Samurai-6M/6MX (ADM6996M/MX) . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.11
Tagged Member Carried through Samurai-6M/6MX (ADM6996M/MX) . . . . . . . . . . . . . . . . . . . .
29
29
29
29
29
29
29
30
30
30
30
31
31
32
32
34
34
35
35
36
36
37
38
38
38
38
38
39
39
39
40
40
40
40
Data Sheet
4
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Table of Contents
3.1.14.12
Egress Tag Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.13
Tagged PRI Carried through Samurai-6M/6MX (ADM6996M/MX) . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.14
CFI Carried through Samurai-6M/6MX (ADM6996M/MX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14.15
Egress TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.15
Priority Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.15.1
System PRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.15.2
Queue Assigned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.15.3
Configure Samurai QoS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.16
Address Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.16.1
Dynamic Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.16.2
Manual Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.16.3
Learning Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.16.3.1
Entry Format in the Learning Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.16.3.2
The Registers Accessing the Learning Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.16.3.3
Rules to Access the Learning Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.16.3.4
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.17
Hardware Based IGMP Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.17.1
Entry Format of IGMP Membership Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.17.2
The Registers Accessing the IGMP Membership Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.17.3
IGMP Snooping Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.18
Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.19
Source Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.20
Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.20.1
Control Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.20.2
Default Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.20.3
Forwarding Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.21
Special TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.21.1
Special Tag for the Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.21.2
Special Tag for the Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Port4 and Port5 MII Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
10/100M PHY Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
Auto Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
Speed/Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Hardware, EEPROM and SMI Interface for Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1
Hardware Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3
SMI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
The Hardware Difference between ADM6996M/MX and ADM6996F . . . . . . . . . . . . . . . . . . . . . . . .
41
42
43
43
43
44
44
46
46
47
47
47
47
48
50
51
51
52
52
53
56
56
58
58
58
58
60
60
62
64
70
71
71
72
72
73
77
79
4
4.1
4.2
4.3
4.4
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EEPROM Basic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
EEPROM Extended Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Counter and Switch Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
5
5.1
5.1.1
5.1.2
5.2
5.3
5.3.1
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX/FX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL/OSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
5
198
198
198
199
199
201
201
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Table of Contents
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
5.3.13
5.3.14
6
6.1
Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMII REFCLK Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RMII REFCLK Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduce MII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPSI (7-wire) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPSI (7-wire) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDC/SDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MDC/MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
202
202
203
205
206
207
207
208
209
210
211
211
212
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Data Sheet
6
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Data Sheet
Samurai-6M/6MX (ADM6996M/MX) Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 TP/FX PORT + 2 MII PORT 128 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Circuit for Single Color LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Circuit for Dual Color LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
To Configure Samurai QoS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ADM6996M/MX to CPU with single MII Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
The configurations of the implementation by ADM6996M/MX Special TAG functions . . . . . . . . . . 65
Software Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ADM6996M/MX to CPU with dual MII Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
100M Full duplex MAC to MAC MII Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PCS to MAC MII connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interconnection between Samurai-6M/6MX (ADM6996M/MX), EEPROM and CPU . . . . . . . . . . . 72
The Power-On-Sequence of Samurai. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Timing Diagram of RC, EECS and EESK (with correct signature EEPROM). . . . . . . . . . . . . . . . . 76
Timing Diagram of RC, EECS and EESK (without EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SMI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
TP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
FX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
XTAL/OSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Power On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
10Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
10Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
100Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
100Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
RMII REFCLK Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
RMII REFCLK Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Reduce MII Timing (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Reduce MII Timing (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
GPSI (7-wire) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
GPSI (7-wire) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
SDC/SDIO Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
MDC/MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
P-PQFP-128 Outside Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Data Sheet
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bandwidth Control Timer Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Smart Disacrd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discard Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Color LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual Color LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packet Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packet Identification Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Span Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Management Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross_VLAN Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VLAN Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VID Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FID Search Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VLAN Boundary Search Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TXTAG Carried through Samurai-6M/6MX (ADM6996M/MX) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Egress Tag Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tagged PRI Carried . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CFI Carried . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Priority Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Queue Assigned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register Description for Accessing the Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description for Command and Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description for the Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register Description for Accessing the IGMP Membership Table . . . . . . . . . . . . . . . . . .
Description for Command and Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Entry Format of IGMP Membership Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPV4/IGMP/General Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPV4/IGMP/V1 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPV4/IGMP/General Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPV4/IGMP/V1 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPV4/IGMP/V2 Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPV4/IGMP/V2 Leave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IPV4/IGMP/Group-Specific Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IGMP Membership Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forwarding Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Tag for the Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Option for Special Tag Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Tag for the Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Set WAN/LAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packets Identified by ADM6996M/MX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed/Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(D) The Pin Type of EECS, EESK, EDI and EDO during the Operation . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
14
14
15
31
31
31
32
34
35
36
36
37
37
38
39
39
39
40
41
42
43
44
44
49
49
49
49
52
52
53
53
54
54
54
54
54
55
56
58
60
62
63
64
65
66
72
73
78
79
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
List of Tables
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
Table 85
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Data Sheet
Pin Description(QFP128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Register Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Registers Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
P1~P5 Basic Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Px_EC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
PxSO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
VFxL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
VFxH Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
TFx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
PFx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
RAx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
TUFx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
CLx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
CHx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
PHY_Cx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
PHY_Sx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
PHY_Ix_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
PHY_Ix_B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
ANAPx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
ANLPAx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
ANEx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
NPTx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
LPNPx Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
DC Electrical Characteristics for 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
XTAL/OSC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Power On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
10Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
10-Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
100Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
100Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
RMII REFCLK Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
RMII REFCLK Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Reduce MII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
GPSI (7-wire) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
GPSI (7-wire) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
SDC/SDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
MDC/MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
9
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Product Overview
1
Product Overview
1.1
Samurai-6M/6MX (ADM6996M/MX) Overview
The Samurai-6M/6MX (ADM6996M/MX) is a high performance, low cost, highly integrated (Controller, PHY and
Memory) four 10M/100M auto-detect Half/Full duplex switch ports with TX/FX interfaces and two MII port with one
MII supporting GPSI/RMII. The Samurai-6M/6MX (ADM6996M/MX) is intended for applications such as stand
alone bridges for the low cost SOHO markets such as 5-port switches and router applications. The Samurai-6MX
(ADM6996MX) is the environmentally friendly “green” package version.
The Samurai-6M/6MX (ADM6996M/MX) provides functions such as: 802.1p(Q.O.S.), 802.1Q(VLAN), Port
MAC address locking, management, port status, TP auto-MDIX, 25M crystal & extra MII port functions to meet
customer requests on switch demand.
The Samurai-6M/6MX (ADM6996M/MX) also supports back pressure in Half-Duplex mode and the 802.3x Flow
Control Pause packet in Full-Duplex mode to prevent packet loss when buffers are full. When Back Pressure is
enabled, and there is no receive buffer available for the incoming packet, the Samurai-6M/6MX (ADM6996M/MX)
will issue a JAM pattern on the receiving port in Half Duplex mode and issue the 802.3x Pause packet back to the
receiving end in Full Duplex mode.
The built-in SRAM used for the packet buffer is divided into 256 bytes per block to achieve the optimized memory
utilization through complicated link lists on packets with various lengths.
The Samurai-6M/6MX (ADM6996M/MX) also supports priority features using Port-Based, VLAN and IP TOS field
checking. Users can easily set different priority modes in individual ports, through a small low-cost micro controller
when initializing or configuring on-the-fly. Each output port supports four queues in the way of fixed N: 1 fairness
queuing to fit the bandwidth demand on various types of packets such as Voice, Video and Data. 802.1Q,
Tag/Untag, and up to 16 groups of VLAN are also supported.
An intelligent address recognition algorithm allows Samurai-6M/6MX (ADM6996M/MX) to recognize up to 2K
different MAC addresses and enables filtering and forwarding at full wire speed.
Port MAC address Locking function is also supported by Samurai-6M/6MX (ADM6996M/MX) to use on building
Internet access to prevent multiple users sharing one port.
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
Supports four 10M/100M auto-detect Half/Full duplex switch ports with TX/FX interfaces and two MII port with
one MII supporting GPSI/RMII
Supports four 10M/100M auto-detect Half/Full duplex switch ports with TX/FX interfaces, one MII port (for CPU
LAN MII) and one isolated PHY(for CPU WAN MII).Five 10M/100M auto-detect Half/Full duplex switch ports
with TX/FX interfaces
2K MAC address tables with 4-ways associative hash algorithm
6KX64 bits packet buffers are divided into 192 blocks of 256 bytes each
Four queues for QoS
Priority features by Port-Based, 802.1p, IP TOS, Diffserv, TCP/UDP Port Application-Based of packets
Store & Forward architecture and performs forwarding and filtering at non-blocking full wire speed
Single/Dual color LED mode with Power On auto diagnostic. Collision/Duplex LED can be separated using
register setting
802.3x Flow Control pause packet for Full Duplex
Back Pressure function for Half Duplex operation
Supports packet lengths up to 1518/1522 (Default)/1536/1784 bytes in maximum
Scalable Per Port Bandwidth Control (Both Ingress and Egress).
Broadcast/Multicast Storm Suppression
Data Sheet
10
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Product Overview
•
•
•
•
•
•
•
•
•
•
•
•
•
802.1Q VLAN. Up to 16 VLAN groups are implemented by full 12 bits VID matching
MAC clone function to enable multiple WAN application
TP interface Auto MDIX function for auto TX/RX swap by strapping-pin.
Interrupt pin, Interrupt Register and Interrupt Mask Register. Programmable interrupt polarity (Default active
low)
Easy Management 32-bit smart counter for per port RX/TX byte/packet count, 16-bit smart counter for per port
ERROR count and Collision count
Supports 32 hardware IGMP Table (Multicast Table)
MAC Address Table is accessible
Supports 802.1x security function
Supports Spanning Tree Protocol
Supports internal counter/PHY status output for management system
25M Crystal
128 QFP package with 0.18 µm technology. 1.8 V/3.3 V power supply.
1.0 W low power consumption.
1.3
Applications
Samurai-6M/6MX (ADM6996M/MX):
•
•
SOHO 5-port switch
5-port switch + Router with 2 MII CPU interface
Data Sheet
11
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Product Overview
1.4
Block Diagram
LED
DISPLAY
CONTROL
LED
Interface
EEPROM
HANDLER
EEPROM
Interface
10/100M
10/100M
MII
Interface
MAC
MAC
Embedded Memory
Memory
BIST
Switching Fabric
10/100M
10/100M
MAC
MAC
...
MII2RMII
MII2GPSI
Twisted
Pair
Interface
MII/RMII/GPSI
Interface
PORT0
PORT1
PORT2
PORT3
DESCRAMBLER
BASE LINE
CORRECTION
FIFO
RXP7
RXN7
A/D
CONVERTER
TXP7
TXN7
DRIVER
BIAS
DIGITAL
EQUALIZER
MLT3
NRZ
NRZI
NRZ
TO
5B
5B
TO
NRZ
JABBER
DETECTOR
DATA
HANDLER
CARRIER INTEGRITY MONITOR
PARTITION HANDLER
SCRAMBLE
R
TRANSMIT
STATE
MACHINE
CLOCK
GENERATOR
Figure 1
Samurai-6M/6MX (ADM6996M/MX) Block Diagram
1.5
Data Lengths
qword: 64 bits
dword: 32 bits
word: 16 bits
byte: 8 bits
nibble: 4 bits
Data Sheet
12
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
2
Interface Description
This chapter describes the interface descriptions for the Samurai-6M/6MX (ADM6996M/MX)
•
•
•
Pin Diagram
Abbreviations
Pin Description by Function
2.1
Pin Diagram
Figure 2 shows the pin diagram for the Samurai-6M/6MX (ADM6996M/MX).
65
66
67
68
69
70
71
IN T_N
P5 TXEN (P H YA S0)
P5 TXC LK /REF CLK _ O UT
P5 RX ER
W AI T _ IN IT
G ND O
VC C3 O
P5 RX CL K/R EFC LK _I N
P4 RX DV
P4 RX D0
VC C2 IK
G ND IK
P4 CR S
P4 CO L
EDI (D UA L C O LO R)
EE CS
EE SK (X OVE N )
VC C2 IK
G ND IK
EDO
CK O 2 5M
CF G0
G ND O
VC C3 O
SPD T N P5
LNKF P5
DP HAL FP 5
P4TXD2
P4TXD1 (P4_BUSMD1)
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
LNKA C T4/ LNK F P4
G ND IK
VC C2 IK
P4TXD3
92
93
94
128
LNKA C T3
126
127
95
124
125
LNKA C T2
122
123
96
121
97
119
120
LNKA C T1
117
118
LNKA C T0
115
116
98
113
114
G ND O
111
112
99
110
100
108
109
P4 RX D1
106
107
P4 RX D2
P4 RX D3
104
105
101
102
103
GNDIK
(GFCEN) P5TXD0
P4FX
(P5_BUSMD0)P5TXD1
(P5_BUSMD1)P5TXD2
P4TXD0 (P4_BUSMD0)
DUPCOL4/DPHALFP4
GNDO
VCC3O
DUPCOL3
DUPCOL2 (BPEN)
DUPCOL1(PHYAS1)
Samurai-M
ADM6996M
DUPCOL0(RECANEN)
P4TXEN
P4TXCLK
VCCIK
P4RXCLK
60
59
58
P5CRS
P5RXD3
57
56
P5RXD2
P5RXD1
55
54
P5RXD0
53
52
P5RXDV
SPDTNP4/LDSPD4
GNDO
VCC3O
LDSPD3
LDSPD2
XI
XO
VCCIK
GNDIK
VCCPLL
GNDPLL
MDC
LDSPD1
CONTROL
VREF
LDSPD0
GNDBIAS
RTX
TEST
MDIO
VCCBIAS
P4RXER
TX P4
V CC A2
36
37
38
35
34
TX N4
33
G N DA
G N DA
32
31
30
29
RX P4
RX N4
V CC AD
RX N3
28
27
RX P3
26
G N DA
G N DA
25
24
TX N3
23
TX P3
V CC A2
22
V CC AD
21
20
RX N2
19
RX P2
G N DA
18
TX N2
17
TX P2
16
14
V CC A2
13
15
RX P1
12
V CC AD
G N DA
11
RX N1
TX N1
G N DA
9
8
10
7
TX P1
V CC AD
6
V CC A2
RX N0
4
5
3
RX P0
G N DA
2
G N DA
TX N0
1
TX P0
V CC A2
Data Sheet
62
61
(SDIO_MD)P5TXD3
P5COL
GNDIK
RC
Figure 2
64
63
51
50
49
48
47
46
45
44
43
42
41
40
39
4 TP/FX PORT + 2 MII PORT 128 Pin Diagram
13
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
2.2
Abbreviations
Standard abbreviations for I/O tables:
Table 1
Abbreviations for Pin Type
Abbreviations
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
AO
Output. Analog levels.
AI/O
Input or Output. Analog levels.
PWR
Power
GND
Ground
MCL
Must be connected to Low (JEDEC Standard)
MCH
Must be connected to High (JEDEC Standard)
NU
Not Usable (JEDEC Standard)
NC
Not Connected (JEDEC Standard)
Table 2
Abbreviations for Buffer Type
Abbreviations
Description
Z
High impedance
PU
Pull up, 10 kΩ
PD
Pull down, 10 kΩ
TS
Tristate capability: The corresponding pin has 3 operational states: Low, high and highimpedance.
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR. An external pull-up is required to sustain the
inactive state until another agent drives it, and must be provided by the central resource.
OC
Open Collector
PP
Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high
(identical to output with no type attribute).
OD/PP
Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with
the OD attribute or as an output with the PP attribute.
ST
Schmitt-Trigger characteristics
TTL
TTL characteristics
2.3
Pin Description by Function
Samurai-6M/6MX (ADM6996M/MX) pins are categorized into one of the following groups:
•
•
•
•
•
•
•
Network Media Connection
Port 4 MII Interface
Port 5 MII Interface
LED Interface
EEPROM Interface
Power/Ground, 48 pins
Miscellaneous
Data Sheet
14
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Note: Table 1 can be used for reference.
Table 3
Ball No.
IO Signals
Name
Pin
Type
Buffer
Type
Function
AI/O
ANA
Receive Pair
Differential data is received on this pin.
AI/O
ANA
AI/O
ANA
AI/O
ANA
MMII_P4RXD0
I
PD,
LVTTL
Port 4 Receive Data Bit 0 in MAC MII Mode
In MAC MII mode, the bit is the LSB of MII receive data,
synchronous to the rising edge of MMII_P4RXCLK.
PMII_P4RXD0
O
8 mA,
PD,
LVTTL
Port 4 Receive Data Bit 0 in PCS MII Mode
When port 4 is operating in PCS MII mode, the bit is the
LSB of MII receive data output and synchronous to the
rising edge of PMII_P4RXCLK.
MMII_P4RXD3
I
PD,
LVTTL
Port 4 Receive Data Bit 3 in MAC MII Mode
In MAC MII mode, this bit is bit[3] of MII receive data, and
synchronous to the rising edge of MMII_P4RXCLK.
PMII_P4RXD3
O
8 mA,
PD,
LVTTL
Port 4 Receive Data Bit 3 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is bit[3]
of MII receive data output and synchronous to the rising
edge of PMII_P4RXCLK.
Network Media Connection
33
RXP_4
29
RXP_3
21
RXP_2
14
RXP_1
6
RXP_0
32
RXN_4
30
RXN_3
22
RXN_2
15
RXN_1
7
RXN_0
37
TXP_4
25
TXP_3
18
TXP_2
10
TXP_1
2
TXP_0
36
TXN_4
26
TXN_3
19
TXN_2
11
TXN_1
3
TXN_0
Transmit Pair
Differential data is transmitted on this pin.
Port 4 MII Interface
74
102
Data Sheet
15
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
101
MMII_P4RXD2
I
PD,
LVTTL
Port 4 Receive Data Bit 2 in MAC MII Mode
In MAC MII mode, this pin is bit[2] of MII receive data, and
synchronous to the rising edge of MMII_P4RXCLK.
PMII_P4RXD2
O
8 mA,
PD,
LVTTL
Port 4 Receive Data Bit 2 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is bit[2]
of MII receive data output and synchronous to the rising
edge of PMII_P4RXCLK.
MMII_P4RXD1
I
PD,
LVTTL
Port 4 Receive Data Bit 1 in MAC MII Mode
In MAC MII mode, this pin is bit[1] of MII receive data, and
synchronous to the rising edge of MMII_P4RXCLK.
PMII_P4RXD1
O
8 mA,
PD,
LVTTL
Port 4 Receive Data Bit 1 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is bit[1]
of MII receive data output and synchronous to the rising
edge of PMII_P4RXCLK.
MMII_P4RXDV
I
PD,
LVTTL
Port 4 Receive Data Valid in MAC MII Mode
Active high to indicate that the data on MMII_P4RXD[3:0] is
valid. Synchronous to the rising edge of MMII_P4RXCLK.
PMII_P4RXDV
O
8 mA,
PD,
LVTTL
Port 4 Receive Data Valid in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is an
active high output signal to indicate PMII_P4RXD[3:0] is
valid. Synchronous to the rising edge of PMII_P4RXCLK.
39
MII_P4RXER
I
PD,
LVTTL
Port 4 Receive Error in MAC MII Mode
Active high to indicate that there is symbol error on the
MII_P4RXD[3:0]. Only valid in 100M operation.
77
MMII_P4CRS
I
PD,
LVTTL
Port 4 Carrier Sense in MAC MII Mode
In full duplex mode, MMII_P4CRS reflects the receive
carrier sense situation on medium only; In Half Duplex,
CRS will be high both in receive and transmit condition.
PMII_P4CRS
O
8 mA,
PD,
LVTTL
Port 4 Carrier Sense in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is used
to output Carrier Sense status.
MMII_P4COL
I
PD,
LVTTL
Port 4 Collision input in MAC MII Mode
Active high to indicate that there is collision on the medium.
Stay low in full duplex operation.
PMII_P4COL
O
8 mA,
PD,
LVTTL
Port 4 Collision output in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is used
to output collision status.
100
73
78
Data Sheet
16
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
106
P4_BUSMD0
I
PD,
LVTTL
Port 4 Bus Type Configuration 0
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) for
Port 4 Configuration Bit 0. Combined with CFG0 and
P4_BUSMD1, Samurai-6M/6MX (ADM6996M/MX)
provides 4 bus type for port 4. See CFG0 pin description for
more details.
Note: Power On Setting
105
MMII_P4TXD0
O
8 mA,
PD,
LVTTL
Port 4 Transmit Data Bit 0 in MAC MII Mode
The LSB bit of MAC MII Transmit data of port 4.
Synchronous to the rising edge of MMII_P4TXCLK.
PMII_P4TXD0
I
PD,
LVTTL
Port 4 Transmit Data Bit 0 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is the
LSB of MII transmit data input and synchronous to the rising
edge of PMII_P4TXCLK.
P4_BUSMD1
I
PD,
LVTTL
Port 4 Bus Type Configuration 1
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) for
Port 4 Configuration Bit 1. Combined with CFG0 and
P4_BUSMD0, Samurai-6M/6MX (ADM6996M/MX)
provides 4 bus type for port 4. See CFG0 for more details.
Note: Power On Setting
103
104
Data Sheet
MMII_P4TXD1
O
8 mA,
PD,
LVTTL
Port 4 Transmit Data Bit 1 in MAC MII Mode
The bit[1] of MAC MII Transmit data of port 4. Synchronous
to the rising edge of MMII_P4TXCLK.
PMII_P4TXD1
I
PD,
LVTTL
Port 4 Transmit Data Bit 1 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is bit[1]
of MII transmit data input and synchronous to the rising
edge of PMII_P4TXCLK.
MMII_P4TXD3
O
8 mA,
PD,
LVTTL
Port 4 Transmit Data Bit 3 in MAC MII Mode
The bit[3] of MAC MII Transmit data of port 4. Synchronous
to the rising edge of MMII_P4TXCLK.
PMII_P4TXD3
I
PD,
LVTTL
Port 4 Transmit Data Bit 3 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is bit[3]
of MII transmit data input and synchronous to the rising
edge of PMII_P4TXCLK.
MMII_P4TXD2
O
8 mA,
PD,
LVTTL
Port 4 Transmit Data Bit 2 in MAC MII Mode
The bit[2] of MAC MII Transmit data of port 4. Synchronous
to the rising edge of MMII_P4TXCLK.
PMII_P4TXD2
I
PD,
LVTTL
Port 4 Transmit Data Bit 2 in PCS MII Mode
When port 4 is operating in PCS MII mode, this pin is bit[2]
of MII transmit data input and synchronous to the rising
edge of PMII_P4TXCLK.
17
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
114
MMII_P4TXEN
O
8 mA,
PD,
LVTTL
Port 4 Transmit Enable in MAC MII Mode
Output by Samurai-6M/6MX (ADM6996M/MX) at the rising
edge of MMII_P4TXCLK when Samurai-6M/6MX
(ADM6996M/MX) is programmed to MAC Type MII.
PMII_P4TXEN
I
PD,
LVTTL
Port 4 Transmit Enable in PCS MII Mode
It is the MII Transmit Enable input to Samurai-6M/6MX
(ADM6996M/MX) when programmed to PCS Type MII.
MMII_P4RXCLK I
PD,
LVTTL
Port 4 Receive Clock in MAC MII Mode
25MHz Free Running clock in 100M Mode and 2.5 MHz
free running clock in 10M Mode. MMII_P4RXDV and
MMII_P4RXD[3:0] should be synchronous to the rising
edge of this clock
PMII_P4RXCLK O
8 mA,
PD,
LVTTL
Port 4 Receive Clock in PCS MII Mode
25MHz Free Running clock in 100M Mode and 2.5 MHz
free running clock in 10M Mode. PMII_P4RXDV and
PMII_P4RXD[3:0] should be synchronous to the rising
edge of this clock
MMII_P4TXCLK I
PD,
LVTTL
Port 4 Transmit Clock in MAC MII Mode
25MHz Free Running clock in 100M Mode and 2.5 MHz
free running clock in 10M Mode. MMII_P4TXEN and
MMII_P4TXD[3:0] should be synchronous to the rising
edge of this clock
PMII_P4TXCLK
O
8 mA,
PD,
LVTTL
Port 4 Transmit Clock in PCS MII Mode
25MHz Free Running clock in 100M Mode and 2.5 MHz
free running clock in 10M Mode. PMII_P4TXEN and
PMII_P4TXD[3:0] should be synchronous to the rising edge
of this clock
P4FX
I
PD,
LVTTL
Port 4 Fiber Selection for PCS MII/PHY mode
During power on reset, value will be latched by Samurai6M/6MX (ADM6996M/MX) at the rising edge of
RESETL(RC) as port 4 Fiber select.
Twisted Pair Mode
0B
1B
Fiber Mode
117
115
62
Data Sheet
18
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
Ball No.
IO Signals (cont’d)
Name
Pin
Type
Buffer
Type
Function
I
PU,
LVTTL
Global Flow Control Enable
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) as
Flow control enable.
Port 5 MII Interface
63
GFCEN
Note: Power On Setting
0B
1B
61
Flow Control Capability is depended upon the
register setting in corresponding port’s Basic Control
Register
All ports flow control capability is enabled
MII_P5TXD0
O
4 mA,
PU,
LVTTL
Port 5 Transmit Data Bit 0 in MII Mode
The LSB bit of MII Transmit data of port 5. Synchronous to
the rising edge of MII_P5TXCLK.
GPSI_P5TXD
O
4 mA,
PU,
LVTTL
Port 5 Transmit Data in GPSI Mode
When port 5 is operating in GPSI mode, this pin acts as
GPSI Transmit Data. Synchronous to the rising edge of
GPSI_P5TXCLK.
RMII_P5TXD0
O
4 mA,
PU,
LVTTL
Port 5 Transmit Data Bit 0 in RMII Mode
When port 5 is operating in RMII mode, this pin acts as RMII
Transmit Data Bit[0]. Synchronous to the rising edge of
REFCLK_IN.
P5_BUSMD0
I
PD,
LVTTL
Port 5 Bus Mode Selection Bit 0
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) as port
5 bus mode selection bit 0. Combined with P5_BUSMD1,
Samurai-6M/6MX (ADM6996M/MX) provides 3 bus types
for port 5. P5_BUSMD[1:0], Interface
Note: Power On Setting
00B
01B
10B
11B
Data Sheet
MII
GPSI
RMII
Reserved and not allowed
MII_P5TXD1
O
4 mA,
PD,
LVTTL
Port 5 Transmit Data Bit 1 in MII Mode
The bit[1] of MII Transmit data of port 5. Synchronous to the
rising edge of MII_P5TXCLK.
RMII_P5TXD1
O
4 mA,
PD,
LVTTL
Port 5 Transmit Data Bit 1 in RMII Mode
The bit[1] of RMII Transmit data of port 5. Synchronous to
the rising edge of REFCLK_IN.
19
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
60
P5_BUSMD1
I
PD,
LVTTL
Port 5 Bus Mode Selection Bit 1
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) as port
5 bus mode selection bit 1. See P5_BUSMD0 for more
details.
Note: Power On Setting
59
MII_P5TXD2
O
4 mA,
PD,
LVTTL
Port 5 Transmit Data Bit 2 in MII Mode
The bit[2] of MII Transmit data of port 5. Synchronous to the
rising edge of MII_P5TXCLK.
SDIO_MD
I
PD,
LVTTL
SDC/SDIO Mode Selection
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) as
SDC/SDIO control signal which is used to select 16 bit
mode.
Note: Power On Setting
0B
66
16 bits mode, MDC/MDIO timing compatible
MII_P5TXD3
O
4 mA,
PD,
LVTTL
Port 5 Transmit Data Bit 3 in MII Mode
The MSB bit of MII Transmit data of port 5. Synchronous to
the rising edge of MII_P5TXCLK.
PHYAS0
I
PD,
LVTTL
PHY Address MSB Bit 0
During power on reset, value will be latched by Samurai6M/6MX (ADM6996M/MX) at the rising edge of
RESETL(RC) as PHY start address select.
PHYAS[1:0] = 00B and PHY address starts from 01000B.
MII_P5TXEN
O
8 mA,
PD,
LVTTL
Port 5 Transmit Enable TXEN in MII Mode
Active high to indicate that the data on MII_P5TXD[3:0] is
valid. Synchronous to the rising edge of MII_P5TXCLK.
GPSI_P5TXEN
O
8 mA,
PD,
LVTTL
Port 5 Transmit Enable TXEN in GPSI Mode
Active high to indicate that the data on GPSI_P5TXD is
valid. Synchronous to the rising edge of GPSI_P5TXCLK.
RMII_P5TXEN
O
8 mA,
PD,
LVTTL
Port 5 Transmit Enable TXEN in RMII Mode
Active high to indicate that the data on RMII_P5TXD[1:0] is
valid. Synchronous to the rising edge of REFCLK_IN.
MII_P5RXD0
I
PD,
LVTTL
Port 5 Receive Data Bit 0 in MII Mode
In MII mode, the bit is the LSB of MII receive data,
synchronous to the rising edge of MII_P5RXCLK.
GPSI_P5RXD
I
PD,
LVTTL
Port 5 Receive Data in GPSI Mode
In GPSI Mode, this acts as Receive Data Input,
synchronous to the rising edge of GPSI_P5RXCLK.
RMII_P5RXD0
I
PD,
LVTTL
Port 5 Receive Data Bit 0 in RMII Mode
In RMII mode, the bit is the LSB of RMII receive data,
synchronous to the rising edge of REFCLK_IN.
Note: Power On Setting
53
Data Sheet
20
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
54
MII_P5RXD1
I
PD,
LVTTL
Port 5 Receive Data Bit 1 in MII Mode
In MII mode, the bit is the bit[1] of MII receive data,
synchronous to the rising edge of MII_P5RXCLK.
RMII_P5RXD1
I
PD,
LVTTL
Port 5 Receive Data Bit 1 in RMII Mode
In RMII mode, the bit is the MSB of RMII receive data,
synchronous to the rising edge of REFCLK_IN.
55
MII_P5RXD2
I
PD,
LVTTL
Port 5 Receive Data Bit 2 in MII Mode
In MII mode, the bit is the bit[2] of MII receive data.
Synchronous to the rising edge of MII_P5RXCLK.
56
MII_P5RXD3
I
PD,
LVTTL
Port 5 Receive Data Bit 3 in MII Mode
In MII mode, the bit is the bit[3] of MII receive data.
Synchronous to the rising edge of MII_P5RXCLK.
52
MII_P5RXDV
I
PD,
LVTTL
Port 5 Receive Data Valid in MII Mode
Active high to indicate that the data on MII_P5RXD[3:0] is
valid. Synchronous to the rising edge of MII_P5RXCLK.
RMII_P5
CRSDV
I
PD,
LVTTL
Port 5 Carrier Sense and Receive Data Valid in RMII
Mode
Active high to indicate that the data on RMII_P5RXD[1:0] is
valid. Synchronous to the rising edge of REFCLK _IN.
MII_P5RXER
I
PD,
LVTTL
Port 5 Receive Error in MII Mode
Active high to indicate that there is symbol error on the
MII_P5RXD[3:0]. Only valid in 100M operation.
RMII_P5RXER
I
PD,
LVTTL
Port 5 Receive Error in RMII Mode
Active high to indicate that there is symbol error on the
RMII_P5 RXD[1:0]. Only valid in 100M operation.
MII_P5CRS
I
PD,
LVTTL
Port 5 Carrier Sense in MII Mode
In full duplex mode, MII_P5CRS reflects the receive carrier
sense situation on medium only; In Half Duplex,
MII_P5CRS will be high both in receive and transmit
condition.
GPSI_P5CRS
I
PD,
LVTTL
Port 5 Carrier Sense in GPSI Mode
In full duplex mode, GPSI_P5CRS reflects the receive
carrier sense situation on medium only; In Half Duplex,
GPSI_P5CRS will be high both in receive and transmit
condition.
MII_P5COL
I
PD,
LVTTL
Port 5 Collision Input in MII Mode
Active high to indicate that there is collision on the medium.
Stay low in full duplex operation.
GPSI_P5COL
I
PD,
LVTTL
Port 5 Collision Input in GPSI Mode
Active high to indicate that there is collision on the medium.
Stay low in full duplex operation.
68
57
58
Data Sheet
21
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
72
MII_P5RXCLK
I
PD,
LVTTL
Port 5 Receive Clock Input in MII Mode
MII_P5RXDV and MII_P5RXD[3:0] are synchronous to the
rising edge of this clock. It is free running 25 MHz clock in
100M mode and 2.5 MHz clock in 10M mode.
GPSI_P5
RXCLK
I
PD,
LVTTL
Port 5 Receive Clock Input in GPSI Mode
GPSI_P5RXD are synchronous to the rising edge of this
clock. It is non-continuous 10 MHz Clock input.
REFCLK_IN
I
PD,
LVTTL
50MHz Reference Clock Input in RMII Mode
RMII_P5RXD[1:0], RMII_P5TXD[1:0], RMII_P5TXEN and
RMII_P5CRSDV are synchronous to the rising edge of this
clock.
MII_P5TXCLK
I
PD,
LVTTL
Port 5 Transmit Clock Input in MII Mode
MII_P5TXEN and MII_P5TXD[3:0] are output at the rising
edge of this clock. It is free running 25 MHz clock in 100M
mode and 2.5 MHz clock in 10M mode.
GPSI_P5
TXCLK
I
PD,
LVTTL
Port 5 Transmit Clock Input in GPSI Mode
GPSI_P5TXEN and GPSI_P5TXD are synchronous to the
rising edge of this clock. It is continuous 10 MHz Clock
input.
REFCLK _ OUT O
8 mA,
PD,
LVTTL
50MHz Reference Clock Output in RMII Mode
This pin is used as 50 MHz reference clock signal output
pin when port 5 operates in RMII mode.
89
SPDTNP5
I
PD,
LVTTL
Port 5 Speed Input
This pin is used to select the speed mode of Port 5.
100M
0B
10M
1B
90
LNKFP5
I
PD,
LVTTL
Port 5 Link Fail Status Input
This pin is used as link control of Port 5.
Link Up
0B
1B
Link Failed
91
DPHALFP5
I
PD,
LVTTL
Port 5 Duplex Status Input
This pin is used to select the duplex mode of Port 5.
Full Duplex
0B
1B
Half Duplex
67
LED Interface
Data Sheet
22
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
107
DPHALFP4
I
PD,
LVTTL
Port 4 Duplex status Input
When Port 4 operates under MAC MII mode (see CFG0 for
more details), this pins is used to select the duplex mode of
Port 4.
0B
Full Duplex
1B
Half Duplex
DUPCOL4
O
8 mA,
PD,
LVTTL
Port 4 Duplex /Collision LED
When Port 4 operates under PHY or PCS MII mode (see
CFG0 for more details), in Full duplex mode, this pin acts
as DUPLEX LED for Port 4; in half duplex mode, it is
collision LED for each port. See Chapter 3.1.12 LED
Display for more details.
110
DUPCOL3
O
8 mA,
PD,
LVTTL
Port 3 Duplex /Collision LED
In Full duplex mode, this pin acts as DUPLEX LED for
Port 3; in half duplex mode, it is collision LED for each port.
See Chapter 3.1.12 LED Display for more details.
111
BPEN
I
PU,
LVTTL
Recommend Back-Pressure in Half-Duplex
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) during power on reset as the backpressure enable in half-duplex mode.
Note: Power On Setting
0B
1B
112
Disable Back-Pressure
Enable Back-Pressure
DUPCOL2
O
8 mA,
PU,
LVTTL
Port 2 Duplex-collision LED
In Full duplex mode, this pin acts as Port 2 DUPLEX LED;
in half duplex mode, it is collision LED for Port 2. See
Chapter 3.1.12 LED Display for more details.
PHYAS1
I
PD,
LVTTL
Recommend PHY Address Bit 1
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) during power on reset as the PHY
address recommends value bit 1. See PHYAS0 description
for more details.
Note: Power On Setting
DUPCOL1
Data Sheet
O
8 mA,
PD,
LVTTL
Port 1 Duplex-collision LED
In Full duplex mode, this pin acts as port 1 DUPLEX LED;
in half duplex mode, it is collision LED for Port 1. See
Chapter 3.1.12 LED Display for more details.
23
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
113
RECANEN
I
PU,
LVTTL
Recommend Auto Negotiation Enable
Only valid for Twisted pair interface. Programmed this bit to
1 has no effect to Fiber port.
Note: Power On Setting.
0B
1B
Disable all TP port auto negotiation capability
Enable all TP port auto negotiation capability
DUPCOL0
O
8 mA,
PU,
LVTTL
Port 0 Duplex-collision LED
In Full duplex mode, this pin acts as port 0 DUPLEX LED;
in half duplex mode, it is collision LED for Port 0. See
Chapter 3.1.12 LED Display for more details.
LNKFP4
I
PD,
LVTTL
Port 4 Link Fail Status Input
When Port 4 operates under MAC MII mode (see CFG0 for
more details), this pin is used as link control of Port 4.
Link Up
0B
Link Failed
1B
LNKACT_4
O
8 mA,
PD,
LVTTL
LINK/Activity LED of Port 4
When Port 4 operates under PHY or PCS MII mode (see
CFG0 for more details), this pin is used to indicate the
link/activity status of Port 4, see Chapter 3.1.12 LED
Display for more details.
95
LNKACT_3
O
96
LNKACT_2
97
LNKACT_1
8 mA,
PD,
LVTTL
LINK/Activity LED of Port 3 to 0
Used to indicate corresponding port' s link/activity status,
see Chapter 3.1.12 LED Display for more details.
98
LNKACT_0
51
SPDTNP4
I
PD,
LVTTL
Port 4 Speed Input
When Port 4 operates under MAC MII mode (see CFG0 for
more details), this pin is used to select the operating speed
of Port 4.
100M
0B
1B
10M
LDSPD_4
O
8 mA,
PD,
LVTTL
Port 4 Speed LED
When Port 4 operates under PHY or PCS MII mode (see
CFG0 for more details), this pin is used to indicate the
speed status of Port 4, see Chapter 3.1.12 LED Display
for more details.
48
LDSPD_3
O
47
LDSPD_2
43
LDSPD_1
8 mA,
PD,
LVTTL
Port 3 to Port 0 Speed LED
Used to indicate corresponding port’ s speed status, see
Chapter 3.1.12 LED Display for more details.
42
LDSPD_0
92
EEPROM Interface
Data Sheet
24
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
84
EDO
I
PU,
LVTTL
EEPROM Data Output
This pin is used to input EEPROM data when reading
EEPROM. During Samurai-6M/6MX (ADM6996M/MX)
initialisation, Samurai-6M/6MX (ADM6996M/MX) will drive
EEPROM interface signal to read settings from EEPROM.
Any other devices attached to EEPROM interface SHOULD
drive Hi-Z or keep tristate during this period. See
Chapter 3.4.2 EEPROM Interface for more details.
80
IFSEL
I
PD,
LVTTL
Interface Selection
After Samurai-6M/6MX (ADM6996M/MX) initialization
process is done, this pin is used to select using EEPROM
interface or SDC/SDIO interface.
EECS/IFSEL interface
SDC/SDIO interface
0B
1B
EEPROM interface
EECS
O
4 mA,
PD,
LVTTL
EEPROM Chip Select
During Samurai-6M/6MX (ADM6996M/MX) initialisation,
this pin is used as EEPROM chip select signal.
During Samurai-6M/6MX (ADM6996M/MX) initialize itself,
Samurai-6M/6MX (ADM6996M/MX) will drive EEPROM
interface signal to read settings from EEPROM. Any other
devices attached to EEPROM interface SHOULD drive HiZ or keep tristate during this period. See Chapter 3.4.2
EEPROM Interface for more details.
XOVEN
I
PD,
LVTTL
Cross Over Enable
Value on this pin (active low) will be latched by Samurai6M/6MX (ADM6996M/MX) at the rising edge of
RESETL(RC) for Port 4~0 crossover auto detect (Only
available in TP interface).
81
Note: Power On Setting.
0B
1B
Data Sheet
Disable
Enable
EESK
I/O
4 mA,
PD,
LVTTL
EEPROM Serial Clock
During Samurai-6M/6MX (ADM6996M/MX) initialisation,
this pin is used to output clock to EEPROM. After Samurai6M/6MX (ADM6996M/MX) initialization process is done,
this pin is used as EEPROM interface clock input if IFSEL
= 1.
SDC
I
PD,
LVTTL
Serial Management interface Clock input
If IFSEL = 0, this pin is used as serial management
interface clock input.
25
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
79
LED_MODE
I
PD,
LVTTL
Enable Mac to Choose LED Display Mode
Value on this pin will be latched by Samurai-6M/6MX
(ADM6996M/MX) at the rising edge of RESETL(RC) as
single/dual color LED mode control signal. See
Chapter 3.1.12 LED Display for more details.
Note: Power On Setting.
EDI
I/O
8 mA,
PD,
LVTTL
EEPROM Serial Data Input
During Samurai-6M/6MX (ADM6996M/MX) initialize itself,
this pin is used to output address and command to access
EEPROM. After the initialization process is done, this pin
becomes an input pin to monitor EEPROM data if IFSEL =
1.
SDIO
I/O
8 mA,
PD,
LVTTL
Serial Management interface Data input/Output
If IFSEL = 0, this pin is used as data input/output pin of
serial management interface.
Power/Ground, 48 Pins
4, 5, 12, 13,
20, 27, 28,
34, 35
GNDA
GND
–
Ground
Used by AD Block
1, 9, 17, 24,
38
VCCA2
PWR
–
1.8 V, Power
Used by TX Line Driver
8, 16, 23, 31 VCCAD
PWR
–
3.3 V, Power
Used by AD Block
126
GNDBIAS
GND
–
Ground
Used by Bias Block
128
VCCBIAS
PWR
–
3.3 V, Power
Used by Bias Block.
123
GNDPLL
GND
–
Ground
Used by PLL
122
VCCPLL
PWR
–
1.8 V, Power
Used by PLL
45, 64, 76,
83, 93, 118
GNDIK
GND
–
Ground
Used by Digital Core
46, 75, 82,
94, 116
VCCIK
PWR
–
1.8 V, Power
Used by Digital Core
50, 70, 87,
99, 108
GNDO
GND
–
Ground
Used by Digital Pad
49, 71, 88,
109
VCC3O
PWR
–
3.3 V, Power
Used by Digital Pad
I
PD,
LVTTL
Test Mode
Reserved and should keep 0 when normal operation.
Miscellaneous
41
Data Sheet
TEST
26
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
86
CFG0
I
PU,
LVTTL
Configuration 0
Combined with P4_BUSMD0 and P4_BUSMD1, Samurai6M/6MX (ADM6996M/MX) provides 3 bus type for port 4.
{CFG0, P4_BUSMD[1:0]}, Bus Mode of Port 4
0_00B PHY Interface
0_01B MAC MII
1_XXB PCS MII
69
WAIT_INIT
I
PD,
LVTTL
Wait Initialization
This pin will be used to pause all activities after power up
until EEPROM is loaded successfully or CPU initialization
is done..
pause until loading EEPROM is done.
0B
1B
pause until EEPROM successfully loaded or CPU
initialization is done.
65
INT_N
O
OD,8 mA Interrupt
Active low interrupt signal to indicate the status change in
the interrupt status register. Interrupt signal will keep active
low until host read the status of ISR register.
Interrupt
0B
Not interrupt
1B
40
MDIO
I/O
8 mA,
PD,
LVTTL
Management Data
MDIO transfers management data in and out of the device
synchronous to MDC.
44
MDC
I
PD, ST
Management Data Reference Clock
A non-continuous clock input for management usage.
Samurai-6M/6MX (ADM6996M/MX) will use this clock to
sample data input on MDIO and drive data onto MDIO
according to rising edge of this clock.
85
CKO25M
O
8 mA,
PD,
LVTTL
25M Clock Output
Free Running 25M Clock output (Even during power on
reset)
119
RC
I
ST
RC Input For Power On Reset
This pin is sampled by using the 25 MHz free running clock
signal which gets the input from XI to generate the lowactive reset signal, RESETL. See Chapter 5.3.2 Power On
Reset for the timing requirements.
120
XI
AI
ANA
25MHz Crystal /Oscillator Input
25MHz Crystal or Oscillator Input. Variation is limited to +/50ppm.
121
XO
AO
ANA
25MHz Crystal Output
When connected to oscillator, this pin should be left
unconnected.
127
RTX
AI
ANA
Constant Voltage Reference
External 1.0 kΩ 1% resistor connection to ground.
Data Sheet
27
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Interface Description
Table 3
IO Signals (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
125
VREF
AI
ANA
Analog Reference Voltage
Used by Internal Bias Circuit for voltage reference.
External 0.1uF capacitor connection to ground for noise
filter.
124
CONTROL
AI/O
ANA
FET Control Signal
The pin is used to control FET for 3.3 V to 1.8 V regulator.
External 0.1uF capacitor connection to ground for noise
filter, even the pin is un-connected.
Data Sheet
28
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Function Description
3
Function Description
3.1
Switch Functional Description
The Samurai-6M/6MX (ADM6996M/MX) uses the “store & forward” switching approach for the following reasons:
1. Store & forward switches allow switching between different speed media (e.g. 10BaseX and 100BaseX). Such
switches require large elastic buffers, especially when bridging between a server on a 100 Mbit/s network and
clients on a 10 Mbit/s segment
2. Store & forward switches improve overall network performance by acting as a “network cache”
3. Store & forward switches prevent the forwarding of corrupted packets by the frame check sequence (FCS)
before forwarding to the destination port
3.1.1
Basic Operation
The Samurai-6M/6MX (ADM6996M/MX) receives incoming packets from one of its ports, uses the source address
(SA) and FID to update the address table, and then forwards the packet to the output ports determined by the
destination address (DA) and FID.
If the DA and FID are not found in the address table, the Samurai-6M/6MX (ADM6996M/MX) treats the packet as
a broadcast packet and forwards the packet to the other ports within the same group.
The Samurai-6M/6MX (ADM6996M/MX) can automatically learn the port number of attached network devices
together with the SA and FID of all the incoming packets. If the SA and FID are not found in the address table, the
Samurai-6M/6MX (ADM6996M/MX) adds it to the table.
3.1.2
Buffers and Queues
The Samurai-6M/6MX (ADM6996M/MX) incorporates 6 transmit queues and receive buffer areas for the 6
Ethernet ports. The receive buffers, as well as the transmit queues, are located within the Samurai-6M/6MX
(ADM6996M/MX) along with the switch fabric. The buffers are divided into 192 blocks of 256 bytes each. The
queues of each port are managed according to each port’s read/write pointer.
Input buffers and output queues are maintained through proprietary patent pending UNIQUE (Universal Queue
management) scheme.
3.1.3
Full Duplex Flow Control
When a full duplex port runs out of its receive buffers, a PAUSE command will be issued by Samurai-6M/6MX
(ADM6996M/MX) to notify the packet sender to pause transmission. This frame based flow control is totally
compliant to IEEE 802.3x. When the flow control hardware pin (GFCEN) is set to high, during power on reset, and
per port PAUSE is enabled, Samurai-6M/6MX (ADM6996M/MX) will output and accept 802.3x flow control
packets.
3.1.4
Half Duplex Flow Control
Back-pressure is supported for half-duplex operation. When the Samurai-6M/6MX (ADM6996M/MX) cannot
allocate a receive buffer for the incoming packet (buffer full), the device will transmit a jam pattern on the port, thus
forcing a collision.
3.1.5
Back-Off Algorithm
The Samurai-6M/6MX (ADM6996M/MX) implements the truncated exponential back off algorithm compliant to the
802.3 standard. Samurai-6M/6MX (ADM6996M/MX) will restart the back off algorithm by choosing 0-9 collision
Data Sheet
29
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Function Description
count. After 16 consecutive retransmit trials, the Samurai-6M/6MX (ADM6996M/MX) resets the collision counter.
Users can set the Back Off (see 0010H, BD) to disable this function.
3.1.6
Inter-Packet Gap (IPG)
IPG is the idle time between any two successive packets from the same port. The value is 9.6 µs for 10 Mbit/s
Ethernet and 960 ns for 100 Mbit/s fast Ethernet. For the receive end, Samurai-6M/6MX (ADM6996M/MX) is
designed to tolerate IPG gaps greater than 64 bits. For the transmit end, Samurai-6M/6MX (ADM6996M/MX) will
always transmit packets with the minimum IPG gap equal to 96 bits. If users want to shorten the transmission IPG
gap, users can enable the Short IPG function (see 000BH, TSIE). Then Samurai-6M/6MX (ADM6996M/MX) will
instruct its output MAC to transmit packets in average 92 bits IPG gap.
3.1.7
Trunking Function
Samurai-6M/6MX (ADM6996M/MX) supports only one trunking port. If Port 3 and Port 4 Trunk (see 000BH, TE)
function is enabled, Samurai-6M/6MX (ADM6996M/MX) will treat Port 3 and Port 4 as the same port to make the
bandwidth equal to 200M. When any of these two ports link fail, the Samurai-6M/6MX (ADM6996M/MX) will
automatically change the transmit path from the failed link port to linked one. Output port based load balancing is
implemented in Samurai-6M/6MX (ADM6996M/MX), without any users’ setting.
3.1.8
Illegal Frames
The Samurai-6M/6MX (ADM6996M/MX) will discard all illegal packets. These packets are
1. Undersized packets: The packets received with the length of less than 64 bytes are discarded
2. Oversized packets: The packets received with the length of more than “MAXPKTLEN” bytes are discarded.
See (0011H, MPL) to see how to set the MAXPKTLEN value
3. CRC packets: The packets received with a wrong FCS value are discarded
4. Symbol error packets: The packets received with symbol error are discarded
5. Source violation packets: The packets received with a source violation could be discarded in some cases. See
(Source Violation) description.
6. VLAN violation packets: The frames received with a VLAN violation can be discarded in some cases. See
(VLAN Violation) description
3.1.9
Broadcast Storm
Samurai-6M/6MX (ADM6996M/MX) allows users to limit the traffic of the broadcast address (DA =
FFFFFFFFFFFFH) to prevent them from blocking the switch bandwidth. If users also want to limit the multicast
packets(DA[40] = 1B), they can set the Multicast Packet Counted into Storming Counter (see 0010H, MP) function.
Two threshold and storm enable bits (see 003BH and 003CH, STORM_EN, STORM_100_TH, STORM_10_TH)
are used to control the broadcast storm.
1. Time Scale. Samurai-6M/6MX (ADM6996M/MX) uses 50ms on a scale to meter the storm packets.
Parameter
Rising Threshold
Falling Threshold
All link ports are 100M
100M Threshold (See 003BH)
1/2 100M Threshold
Not All link ports are 100M
10M Threshold (See 003CH)
1/2 10M Threshold
2. Storm keeps on at least 1.6 seconds if any of the ports meet the rising threshold in the 4 consecutive 50 ms
intervals. In these 1.6 seconds, the ports meet the rising threshold and will start to discard the broadcast or
multicast packets until the 50 ms interval expires. Users could also disable Input Filter (see 000BH, IF) function to
forward above packets to the un-congested port instead of discarding directly.
3. Storm finishes. After the 1.6-second storm period, Samurai-6M/6MX (ADM6996M/MX) will check the port that
makes the storm on. If all of these ports meet the falling threshold in the 2 consecutive 50 ms intervals and no
Data Sheet
30
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Function Description
other ports meet the rising threshold at the same time, Samurai-6M/6MX (ADM6996M/MX) will treat it the storm
has finished.
3.1.10
Bandwidth Control
Samurai-6M/6MX (ADM6996M/MX) supports hardware-based bandwidth control for both ingress and egress
traffic. Ingress and egress rate can be limited independently on each port base. The Samurai-6M/6MX
(ADM6996M/MX) provides several timer scales corresponding to different the bandwidth control unit, so users can
configure the rate equal to K * (Bandwidth Step), 1 one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
lhsc
Latches high signal at high level,
cleared on read
SW can read the register
Latch low,
self clearing
llsc
Latches high signal at low-level,
cleared on read
SW can read the register
Latch high,
mask clearing
lhmk
Latches high signal at high level,
register cleared with written mask
SW can read the register, with write mask
the register can be cleared (1 clears)
Latch low,
mask clearing
llmk
Latches high signal at low-level,
register cleared on read
SW can read the register, with write mask
the register can be cleared (1 clears)
Interrupt high,
self clearing
ihsc
Differentiates the input signal (low>high) register cleared on read
SW can read the register
Interrupt low,
self clearing
ilsc
Differentiates the input signal (high>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
ihmk
Differentiates the input signal (highSW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Interrupt low,
mask clearing
ilmk
Differentiates the input signal (low>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
Enables the interrupt source for
interrupt generation
SW can read and write this register
latch_on_reset
lor
rw register, value is latched after first
clock cycle after reset
Register is readable and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
signal for the HW (1 pdi clock cycle)
mechanism.
Register is readable and writable by SW.
Table 54
Registers Clock Domains
Clock Short Name
Description
–
–
Data Sheet
89
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
4.1
EEPROM Basic Registers
Signature Register
SIG
Signature Register
Offset
00H
Reset Value
4154H
6,*
UR
Field
Bits
Type
Description
SIG
15:0
ro
Signature
The value must be 4154H . Samurai-6M/6MX (ADM6996M/MX) uses this
value to check if EEPROM is attached. If the value in the EEPROM is not
equal to 4154H , Samurai-6M/6MX (ADM6996M/MX) will stop loading the
EEPROM even if EEPROM is attached and Samurai-6M/6MX
(ADM6996M/MX) will use the default value inside the chip to initialize.
P0 Basic Control Register
P0BC
P0 Basic Control Register
&526 6(/)
6B(( ;B((
UZ
UZ
Data Sheet
Offset
01H
Reset Value
040FH
39,'B
33
33(
,39/
$1
3'
237(
'$
6$
$1(
)&(
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
90
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
CROSS_EE
15
rw
Crossover Auto Detect Enable
This bit is used together with the value (cross_hw) on the pin EESK/SDC
during the power on reset and the value (wait_init) on the pin WAIT_INIT
during the normal mode to decide if PHY enables this function. This bit is
useless in Port 5.
Combine with wait_initand cross_hw, the crossover auto detect capability
is summarized as below :
{wait_init, cross_hw, cross_ee} Description
1x1B This port will enable Crossover Auto Detect Enable function
1x0B This port will disable Crossover Auto Detect Enable function
01xB This port will enable Crossover Auto Detect Enable function
000B This port will disable Crossover Auto Detect Enable function
001B This port will enable Crossover Auto Detect Enable function
SELFX_EE
14
rw
Select FX
This bit is used together with the value (p4fx_hw) on the pin P4FX during
the power on reset to decide if the PHY operates on the fiber mode. This
bit is useless in Port 5. Port 0, 1, 2, 3: follow selfx_ee Description and Port
4: follow {p4fx_hw, selfx_ee} Description
1xB Port 4: Port 4 will operate in the fiber mode
00B Port 4: Port 4 will operate in the twisted mode
01B Port 4: Port 4 will operate in the fiber mode
PVID3_0
13:10
rw
Private VID
See 0028H ~ 002CH to find the other PVID [11:4]
PP
9:8
rw
Port Priority
00B Assign packets to Queue 0
01B Assign packets to Queue 1
10B Assign packets to Queue 2
11B Assign packets to Queue 3
PPE
7
rw
Port Priority Enable
0B
The port priority is disabled
The port priority is enabled
1B
IPVLAN
6
rw
IP over VLAN PRI
0B
Use the priority bits in the tag header to assign the priority queue
1B
Use the IP PRI to assign the priority queue
PD
5
rw
Port Disable
Port 0, 1, 2, 3, 4: PHY works normally. Port 5: Port 5 works normally
0B
1B
Port 0, 1, 2, 3, 4. PHY is disabled. Port 5: Port 5 is forced to link
down
OPTE
4
rw
Output Packet Tagging Enable
Untagged packets are transmitted
0B
Tagged packets are transmitted
1B
DA
3
rw
Duplex Ability
It is useless in Port 5.
Recommend PHY to work in the half duplex mode
0B
Recommend PHY to work in the full duplex mode
1B
Data Sheet
91
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
SA
2
rw
Speed Ability
It is useless in Port 5.
Recommend PHY to work in the 10M mode
0B
1B
Recommend PHY to work in the 100M mode
ANE
1
rw
Auto Negotiation Enable
It is useless in Port 5.
Recommend PHY to work without Auto Negotiation
0B
1B
Recommend PHY to work with Auto Negotiation, when the value
on the pin DUPCOL0 during the power on reset is 1
FCE
0
rw
Flow Control Enable
Recommend MAC to work without Pause or Back Pressure
0B
1B
In full duplex, recommend MAC to work with Pause when the value
on the TXD0 during the power on reset is 1. In half duplex,
recommend MAC to work with Back Pressure when the value on
the DUPCOL2 during the power on reset is 1
Similar Registers
Table 55
P1~P5 Basic Control Registers
Register Short Name
Register Long Name
Offset Address
P1BC
P1 Basic Control Register
03H
P2BC
P2 Basic Control Register
05H
P3BC
P3 Basic Control Register
07H
P4BC
P4 Basic Control Register
08H
P5BC
P5 Basic Control Register
09H
Page Number
P0 Extended Control Register
P0EC
P0 Extended Control Register
5HV
U
$' /'
UZ
Offset
02H
01$
5HV
UZ
U
UZ
Reset Value
0000H
$' /'
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
AD135
14
rw
Aging Disable
P1, P3, and P5.
Aging function is enabled
0B
1B
Aging function is disabled
Data Sheet
92
UZ
01$
UZ
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
LD135
13
rw
Learning Disable
P1, P3, and P5.
Learning function is enabled
0B
1B
Learning function is disabled
MNA135
12:8
rw
Maximum Number of Addresses
Learned from the port (P1, P3, and P5).
Note: set value to Others = limit the number of addresses to be learned.
00000B
Doesn’t limit the number of addresses to be learned
Res
7
r
Reserved
AD024
6
rw
Aging Disable
P0, P2, and P4.
Aging function is enabled.
0B
Aging function is disabled.
1B
LD024
5
rw
Learning Disable
P0, P2, and P4.
0B
Learning function is enabled.
Learning function is disabled.
1B
MNA024
4:0
rw
Maximum Number of Addresses
Learned from the port (P0, P2, and P4).
Note: set value to Others = limit the number of addresses to be learned.
00000B
Doesn’t limit the number of addresses to be learned
Similar Registers
Table 56
Px_EC Registers
Register Short Name
Register Long Name
Offset Address
P1EC
P1 Extended Control Register
02H
P2EC
P2 Extended Control Register
04H
P3EC
P3 Extended Control Register
04H
P4EC
P4 Extended Control Register
06H
P5EC
P5 Extended Control Register
06H
Page Number
System Control Register 0
SC0
System Control Register 0
Offset
0AH
(5&037+
3&5
3&(
UZ
UZ
UZ
Data Sheet
59,' 59,' 59,'
)))
UZ
UZ
UZ
93
Reset Value
5902H
'),'
177(
78
30
UZ
UZ
UZ
UZ
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
ERCMPTH
15:12
rw
Earlier Cycles for Transmission
It means the earlier cycles for transmission used in Samurai-6M/6MX
(ADM6996M/MX). It is for the engineer debug purpose.
PCR
11
rw
Priority Change Rule
0B
Use VLAN_PRI field in the matched VLAN filter
Reverse PRI in the same way as untagged packet
1B
PCE
10
rw
Priority Change Enable
0B
Do not change the priority in the tag header
1B
Change the priority field in the tag header
RVID0
9
rw
Replace VID0
Do not replace
0B
1B
Replace
RVID1
8
rw
Replace VID1
Do not replace
0B
1B
Replace
RVIDFFF
7
rw
Replace VIDFFF
Do not replace
0B
1B
Replace
DFID
6:3
rw
Default FID
See Chapter 3.1.14.7 FID and VLAN Boundary for more detailed
information.
NTTE
2
rw
New Transmit Tag Enable
Use old
0B
Use new
1B
TU
1
rw
TOS Using
0B
Use the most significant 6 bits of the TOS field in the IPV4 header
to map the priority queue
Use the most significant 3 bits of the TOS field in the IPV4 header
1B
to map the priority queue
PM
0
rw
PPPOE Manage
When the port is configured as PPPOE Only, the port will only transmit
the PPPOE packets. But when the packet is a management one, users
could configure PPPOE Manage to 1B to transmit this packet on the
PPPOE Only port even if it is not a PPPOE packet. Samurai-6M/6MX
(ADM6996M/MX) identifies packets with Ether-Type = 8863H or 8864H as
the PPPOE packet.
System Control Register 1
SC1
System Control Register 1
Data Sheet
Offset
0BH
94
Reset Value
8001H
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
')()
'
,)
UZ
UZ
$6&
6,&
6,0
6,$
&06
7(
UZ
UZ
UZ
UZ
UZ
UZ
76,( &3'& 6925 692$ 6926 692' 1(
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
DFEFD
15
rw
Disable Far-End-Fault Detection
0B
Far-End-Fault detect ion is enabled
Far-End-Fault detect ion is disabled
1B
IF
14
rw
Input Filter
0B
Discardes packets directly when storming or the lack of input
buffers
Forwardes packets to the un-congested port when storming or the
1B
lack of input buffers
ASC
13:12
rw
Additional Snooping Control
These bits are used when the packets on the incoming port with the
Ethernet destination address = 01005ExxxxxxH/3333xxxxxxH are not
IGMP_IP/ MLD_IPV/MLD_IPV6 packets and not found in the learning
table or the hardware IGMP table.
00B As normal multicast packets
01B Dropped
10B Send to CPU if the receiving port is non-CPU port or send to
Multicast Portmap if the receiving is the CPU port
11B Reserved
SIC
11
rw
Source Intrusion Condition
0B
Learning table source violation does not consider the port match
Learning table source violation takes the port match into
1B
consideration
SIM
10
rw
Source Intrusion Must
Learning table source violation will be effective in the following
0B
conditions. (1) The packets are not the management packets. (2)
The packets are the management packets but Source Violation
Over Reserve (SVOR) is 1B
1B
Must follow the learning table source violation rules
SIA
9
rw
Source Intrusion Action
0B
Discarded
1B
Send to the CPU port
CMS
8
rw
Carrier Mask Select (Reserved for test)
Mask CRS of 4 Cycles
0B
1B
Mask CRS of 5 Cycles
TE
7
rw
Port 3 and Port 4 Trunk Enable
No trunk is enabled
0B
1B
Port 3 and Port 4 are trunked
TSIE
6
rw
Transmit Short IPG Enable
96 bits time of IPG is used
0B
1B
88/96 bits time of IPG is used
Data Sheet
95
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
CPDC
5
rw
CPU Port Doesn’ t Check
CPU Port doesn’ t check CRC, for packets with Special Tag.
Checks
0B
1B
Doesn’t Check
SVOR
4
rw
Source Violation Over Reserve
This bit is used when the management packet with DA = 0180C20000xxH
violates the source rule.
0B
Source violation doesn’t change the forwarding algorithm
Source violation will change the forwarding algorithm
1B
SVOA
3
rw
Source Violation Over ARP/RARP
This bit is used when the ARP/RARP packet classified as management
that violates the source rule.
Source violation doesn’t change the forwarding algorithm
0B
1B
Source violation will change the forwarding algorithm
SVOS
2
rw
Source Violation Over Snooping
This bit is used when the MLD_IPV6/MLD_IP/IGMP/IP packet classified
as management that violates the source rule.
Source violation doesn’t change the forwarding algorithm
0B
Source violation will change the forwarding algorithm
1B
SVOD
1
rw
Source Violation Over Default
This bit is used when the packet that is not the same as the above and it
is classified as management that violates the source rule.
Source violation doesn’t change the forwarding algorithm
0B
1B
Source violation will change the forwarding algorithm
NE
0
rw
New EEPROM
Use old EEPROM functions
0B
1B
New EEPROM function is enabled
Multicast Snooping Register
MS
Multicast Snooping Register
Offset
0CH
6&3$
6&33
(
6&33
6&377+
UZ
UZ
UZ
UZ
Data Sheet
Reset Value
0000H
6&37 6&37 6&37 70,
70,3
&
0
6
3
UZ
UZ
96
UZ
UZ
UZ
7,3
UZ
+,3, +,6(
UZ
UZ
+,'5
(
UZ
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
SCPA
15:14
rw
Snooping Control Packet Action
00B IGMP Portmap is 000000B
01B IGMP Portmap is the Multicast Portmap
10B If the incoming port is not the CPU port, then the IGMP Portmap is
the CPU port. If the incoming port is the CPU port, then the IGMP
Portmap is the Multicast Portmap except the CPU port
11B If the incoming port is not the CPU port, then the Multicast Portmap
is the CPU port. If the incoming port is the CPU port, then the
Multicast Portmap is the default output ports except the CPU port
SCPPE
13
rw
Snooping Control Packet Priority Enable
Disable
0B
Enable
1B
SCPP
12:11
rw
Snooping Control Packet Priority
00B Queue 0
01B Queue 1
10B Queue 2
11B Queue 3
SCPTTH
10:9
rw
Snooping Control Packet Transmission Tag Handle
00B System Default Tag
01B Unmodified
10B Always Tagged
11B Always Untagged
SCPTC
8
rw
Snooping Control Packet Treated as Cross_VLAN Packet
0B
Doesn’t identify
Identifies as the cross_VLAN packet
1B
SCPTM
7
rw
Snooping Control Packet Treated as Management Packet
0B
Doesn’t identify
Identifies as the management packet
1B
SCPTS
6
rw
Snooping Control Packet Treated as Span Packet
Doesn’t identify
0B
Identifies as the span packet
1B
TMI6P
5
rw
Trap MLD_IPV6 Packet
Doesn’t trap
0B
1B
Traps
TMIP
4
rw
Trap MLD_IP Packet
Doesn’t trap
0B
1B
Traps
TIP
3
rw
Trap IGMP_IP Packet
0B
Doesn’t Trap
Trasp
1B
HIPI
2
rw
Hardware IGMP Packet Ignore CPU Port
0B
IGMP packet forwards to CPU also when Hardware IGMP
Snooping is enabled
IGMP packet doesn’t forward to CPU when Hardware IGMP
1B
Snooping is enabled
Data Sheet
97
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
HISE
1
rw
Hardware IGMP Snooping Enable
0B
Disable Hardware IGMP Snooping
Enable Hardware IGMP Snooping
1B
HIDRE
0
rw
Hardware IGMP Default Router Enable
0B
Disable
Enable
1B
Data Sheet
98
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
ARP/RARP Register
AR
ARP/RARP Register
Offset
0DH
Reset Value
0000H
5HV
,03
837
537
5$3$
5$33
(
5$33
5$327+
$37
U
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
5$37 7$37
7$3
0
6
UZ
UZ
UZ
753
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
IMP
14
rw
IP Multicast Packet Treated as Cross_VLAN packet
Doesn’t identify
0B
1B
Identifies as the cross_VLAN packet
UPT
13
rw
Unicast packet Treated as Cross_VLAN packet
Doesn’t identify
0B
1B
Identifies as the cross_VLAN packet when there is a match in the
learning table
RPT
12
rw
R ARP Packet Treated as Cross_VLAN Packet
Doesn’t identify
0B
1B
Identifies as the cross_VLAN packet
RAPA
11:10
rw
RARP/ARP Packet Action
00B ARP/RARP Portmap is 000000B
01B ARP/RARP Portmap is the Broadcast Portmap
10B If the incoming port is not the CPU port, then the ARP/RARP
Portmap is the CPU port. If the incoming port is the CPU port, then
the ARP/RARP Portmap is the Broadcast Portmap except the CPU
port
11B If the incoming port is not the CPU port, then the ARP/RARP
Portmap is the CPU port. If the incoming port is the CPU port, then
the ARP/RARP Portmap is the default output port except the CPU
port
RAPPE
9
rw
RARP/ARP Packet Priority Enable
Disable
0B
1B
Enable
RAPP
8:7
rw
RARP/ARP Packet Priority
00B Queue 0
01B Queue 1
10B Queue 2
11B Queue 3
Data Sheet
99
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
RAPOTH
6:5
rw
RARP/ARP Packet Output Tag Handle
00B System Default Tag
01B Unmodified
10B Always Tagged
11B Always Untagged
APT
4
rw
ARP Packet Treated as Cross _ VLAN Packet
Doesn’t identify
0B
1B
Identifies as the cross_VLAN packet
RAPTM
3
rw
RARP/ARP Packet Treated as Management Packet
Doesn’t identify
0B
1B
Identifies as the management packet
TAPTS
2
rw
RARP/ARP Packet Treated as Span Packet
Doesn’t identify
0B
1B
Identifies as the span packet
TAP
1
rw
Trap ARP Packet
0B
Doesn’t Trap
Traps
1B
TRP
0
rw
Trap RARP Packet
0B
Doesn’t Trap
Traps
1B
VLAN Priority Map Register
VPM
VLAN Priority Map Register
Offset
0EH
Reset Value
FA50H
34
34
34
34
34
34
34
34
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PQ7
15:14
rw
Priority Queue 7
These 2 bits are used as the priority queue when the tagged packets with
the user priority = 111B are received on the port.
00B Queue 0
01B Queue 1
10B Queue 2
11B Queue 3
PQ6
13:12
rw
Priority Queue 6
These 2 bits are used as the priority queue when the tagged packets with
the user priority = 110B are received on the port.
Data Sheet
100
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
PQ5
11:10
rw
Priority Queue 5
These 2 bits are used as the priority queue when the tagged packets with
the user priority = 101B are received on the port.
PQ4
9:8
rw
Priority Queue 4
These 2 bits are used as the priority queue when the tagged packets with
the user priority = 100B are received on the port.
PQ3
7:6
rw
Priority Queue 3
These 2 bits are used as the priority queue when the tagged packets with
the user priority = 011B are received on the port.
PQ2
5:4
rw
Priority Queue 2
These 2 bits are used as the priority queue when the tagged packets with
the user priority = 010B are received on the port.
PQ1
3:2
rw
Priority Queue 1
These 2 bits are used as the priority queue when the tagged packets with
the user priority = 001B are received on the port.
PQ0
1:0
rw
Priority Queue 0
These 2 bits are used as the priority queue when the tagged packets with
the user priority = 000B are received on the port.
TOS Priority Map Register
TPM
TOS Priority Map Register
Offset
0FH
Reset Value
FA50H
34
34
34
34
34
34
34
34
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PQ7
15:14
rw
Priority Queue 7
These 2 bits are used as the priority queue, when the most significant 3
bits in the TOS field are 111B
00B Queue 0
01B Queue 1
10B Queue 2
11B Queue 3
PQ6
13:12
rw
Priority Queue 6
These 2 bits are used as the priority queue, when the most significant 3
bits in the TOS field are 110B
PQ5
11:10
rw
Priority Queue 5
These 2 bits are used as the priority queue, when the most significant 3
bits in the TOS field are 101B
Data Sheet
101
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
PQ4
9:8
rw
Priority Queue 4
These 2 bits are used as the priority queue, when the most significant 3
bits in the TOS field are 100B
PQ3
7:6
rw
Priority Queue 3
These 2 bits are used as the priority queue, when the most significant 3
bits in the TOS field are 011B
PQ2
5:4
rw
Priority Queue 2
These 2 bits are used as the priority queue, when the most significant 3
bits in the TOS field are 010B
PQ1
3:2
rw
Priority Queue 1
These 2 bits are used as the priority queue, when the most significant 3
bits in the TOS field are 001B
PQ0
1:0
rw
Priority Queue 0
These 2 bits are used as the priority queue, when the most significant 3
bits in the TOS field are 000B
System Control Register 2
SC2
System Control Register 2
Offset
10H
Reset Value
0040H
'0B4
'0B4
'0B4
'0B4
$'
&&
03
&&'
%'
6(
67
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
DM_Q3
15:14
rw
Discard Mode Q3
Discard Mode (Drop scheme for Packets Classified as Q3) . See
Chapter 3.1.11 Smart Discard for more detail information.
DM_Q2
13:12
rw
Discard Mode Q2
Discard Mode (Drop scheme for Packets Classified as Q2) . See
Chapter 3.1.11 Smart Discard for more detail information.
DM_Q1
11:10
rw
Discard Mode Q1
Discard Mode (Drop scheme for Packets Classified as Q1) . See
Chapter 3.1.11 Smart Discard for more detail information.
DM_Q0
9:8
rw
Discard Mode Q0
Discard Mode (Drop scheme for Packets Classified as Q0) . See
Chapter 3.1.11 Smart Discard for more detail information.
AD
7
rw
Aging Disable
Useless in Samurai-6M/6MX (ADM6996M/MX)
Age enabled
0B
1B
Age disabled
Data Sheet
102
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
CC
6
rw
Rx Clock Change to Tx Clock for GPSI Interface
0B
Samurai-6M/6MX (ADM6996M/MX) does not use Tx clock to
replace Rx clock when Rx clock stops.
Samurai-6M/6MX (ADM6996M/MX) uses Tx clock to replace Rx
1B
clock when Rx clock stops
MP
5
rw
Multicast Packet Counted into the Storm Counter
Only broadcast packets are counted into the storming counter
0B
1B
Multicast and broadcast packets are counted into the storming
counter
CCD
4
rw
CRC Check Disable
Checks CRC
0B
1B
Doesn’t check CRC
BD
3
rw
Back Off Disable
Back-off is enabled
0B
1B
Back-off is disabled
SE
2
rw
Storming Enable
It is used in ADM6996L/F style storm control.
Disable broadcast/multicast storm protection.
0B
Enable boradcast/multicast storm protection.
1B
ST
1:0
rw
Storming Threshold[1:0]
It is used in ADM6996L/F style storm control.
System Control Register 3
SC3
System Control Register 3
&31
Offset
11H
675( 677(
UZ
UZ
UZ
Reset Value
E300H
3
03/
16(
UZ
UZ
UZ
7%9 0&(
UZ
Field
Bits
Type
Description
CPN
15:13
rw
CPU Port Number
000B The CPU is attached to Port 0
001B The CPU is attached to Port 1
010B The CPU is attached to Port 2
011B The CPU is attached to Port 3
100B The CPU is attached to Port 4
101B The CPU is attached to Port 5
111B No CPU exists
Data Sheet
103
UZ
42
,3,
$76
UZ
UZ
UZ
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
STRE
12
rw
Special TAG Receive Enable
Samurai-6M/6MX (ADM6996M/MX) doesn’t identify the Special
0B
TAG for the incoming packets
Samurai-6M/6MX (ADM6996M/MX) identifies the Special TAG for
1B
the incoming packets
STTE
11
rw
Special TAG Transmit Enable
Samurai-6M/6MX (ADM6996M/MX) does not insert Special TAG
0B
for the packets transmitted to the CPU port
Samurai-6M/6MX (ADM6996M/MX) inserts Special TAG for the
1B
packets transmitted to the CPU port.
P
10
rw
Pause
Also adds Special Tag when Special TAG Transmit is enabled .
Does not add Special Tag on the PAUSE packets
0B
1B
Adds Special Tag in the PAUSE packets
MPL
9:7
rw
Max Packet Length
000B 1518 bytes
001B 1536 bytes
010B 1664 bytes
110B 1522 bytes
x11B 1784 bytes
10xB 1784 bytes
NSE
6
rw
New Storming Enable
Uses the ADM6996L/F style storming control
0B
1B
Uses the Samurai-6M/6MX (ADM6996M/MX) style storming
control
TBV
5
rw
Tag Base VLAN
Port VLAN
0B
Tagged VLAN
1B
MCE
4
rw
MAC Clone Enable
MAC Clone is disabled
0B
1B
MAC Clone is enabled
QO
3
rw
Queue Option
It’ s the test for the designer in the queue control.
IPI
2
rw
Interrupt Polarity Inverter
The interrupt signal is active pull low
0B
The interrupt signal is active pull high
1B
ATS
1:0
rw
Aging Timer Select
00B 300 Seconds
01B 75 Seconds
10B 18 Seconds
11B 1 Second
System Control Register 4
SC4
System Control Register 4
Data Sheet
Offset
12H
104
Reset Value
3600H
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
'3
'83B
&2/
UZ
UZ
5HV
7/(
5HV
UZ
UZ
UZ
5HV 2)/ 2)/ 2)/
UZ
UZ
UZ
UZ
3,
2)/
UZ
UZ
'8$/
2)/ /('
2)/
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
DP
15
rw
Drop Packet When Excessive Collision Happen
0B
Doesn’t drop
Drops
1B
DUP_COL_SE 14
P
rw
Duplex and Col Separate
0B
Indicates the duplex and collision status at the same time
Indicates the duplex status only
1B
Res
13:12
rw
Reserved
TLE
11
rw
Ten Limit Enable
This function works only when Full Flow Control/Half Back Pressure is
enabled.
The switch will not ignore 10 Mbit/s paths even when the ten limit
0B
reaches
The switch will forward packets with Multicast, Broadcast, or
1B
Unicast but not learned DA addresses from 100 Mbit/s only to 100
Mbit/s ports and ignore the 10M paths when the ten limit reaches.
This function allows the switch to balance the high and the low
speed
Res
10
rw
Reserved
Res
9
rw
Reserved
O5FL
8
rw
OLD P5 First Lock
First Lock is disabled
0B
1B
First Lock is enabled
O4FL
7
rw
OLD P4 First Lock
First Lock is disabled
0B
1B
First Lock is enabled
O3FL
6
rw
OLD P3 First Lock
First Lock is disabled
0B
1B
First Lock is enabled
PI
5
rw
Pause Ignore
0B
Doesn’t ignore Pause packets
Ignores Pause packets in half duplex or in full duplex when flow
1B
control is not enabled
O2FL
4
rw
OLD P2 First Lock
First Lock is disabled
0B
1B
First Lock is enabled
DUALCOLOR-EE
3
rw
Dual Color in MDC / MDIO with CPU
See Chapter 3.1.12 LED Display for more detailed information.
Single Color
0B
1B
Dual Color
Data Sheet
105
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
O1FL
2
rw
OLD P1 First Lock
First Lock is disabled
0B
First Lock is enabled
1B
LED-ENABLE
1
rw
LED Enable
0B
Disable
Enable
1B
O0FL
0
rw
OLD P0 First Lock
0B
First Lock is disabled
1B
First Lock is enabled
Port 0 Security Option
Port Spanning Tree State and Forward Group Port Map.
P0SO
Port 0 Security Option
Offset
13H
5HV
&3
362
U
UZ
UZ
Reset Value
01D5H
6736
3
3
3
5HV
3
5HV
3
5HV
3
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
CP
14
rw
Close Port
Doesn’t close the port
0B
1B
When port security exists, the port is closed automatically
PSO
13:11
rw
Port Security Option
001B Unknown to CPU
010B Discard Unknown
011B First Lock
100B First Link Lock
101B Assign Lock
110B Assign Link Lock
Data Sheet
106
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
STPS
10:9
rw
Spanning Tree Port Status
The Samurai-6M/6MX (ADM6996M/MX) supports 4 port status to support
Spanning Tree Protocol .
00B Forwarding State. The port acts as the normal mode
01B Disabled State . The port entity will not transmit and receive any
packets. Learning is disabled in this state
10B Learning State . The port entity will only transmit and receive span
packets. All other packets are discarded. Learning is enabled for all
good frames
11B Blocking/Listening. Only the span packets defined by Samurai6M/6MX (ADM6996M/MX) will be received and transmitted. All
other packets are discarded by the port entity. Learning is disabled
in this state
P5
8
rw
Port 5 is a Member of the Forwarding Group
Port 5 is not a member
0B
1B
Port 5 is a member
P4
7
rw
Port 4 is a Member of the Forwarding Group
0B
Port 4 is not a member
Port 4 is a member
1B
P3
6
rw
Port 3 is a Member of the Forwarding Group
0B
Port 3 is not a member
Port 3 is a member
1B
Res
5
r
Reserved
P2
4
rw
Port 2 is a Member of the Forwarding Group
0B
Port 2 is not a member
Port 2 is a member
1B
Res
3
r
Reserved
P1
2
rw
Port 1 is a Member of the Forwarding Group
0B
Port 1 is not a member
Port 1 is a member
1B
Res
1
r
Reserved
P0
0
rw
Port 0 is a Member of the Forwarding Group
0B
Port 0 is not a member
Port 0 is a member
1B
Similar Registers
Table 57
PxSO Registers
Register Short Name
Register Long Name
Offset Address
P1SO
Port 1 Security Option
14H
P2SO
Port 2 Security Option
15H
P3SO
Port 3 Security Option
16H
P4SO
Port 4 Security Option
17H
P5SO
Port 5 Security Option
18H
Data Sheet
107
Page Number
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Unicast Port Map and Forward Group Port Map
UFGPM
Unicast Port Map andForward Group Port
Map
Offset
19H
Reset Value
FFD5H
5HV
83
3
3
3
5HV
3
5HV
3
5HV
3
U
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
UP
14:9
rw
Unicast Portmap
See Chapter 3.1.20 Packet Forwarding for more detailed information.
P5
8
rw
Port 5 is a Member of the Forwarding Group
Port 5 is not a member
0B
1B
Port 5 is a member
P4
7
rw
Port 4 is a Member of the Forwarding Group
0B
Port 4 is not a member
Port 4 is a member
1B
P3
6
rw
Port 3 is a Member of the Forwarding Group
0B
Port 3 is not a member
Port 3 is a member
1B
Res
5
r
Reserved
P2
4
rw
Port 2 is a Member of the Forwarding Group
0B
Port 2 is not a member
Port 2 is a member
1B
Res
3
r
Reserved
P1
2
rw
Port 1 is a Member of the Forwarding Group
0B
Port 1 is not a member
Port 1 is a member
1B
Res
1
r
Reserved
P0
0
rw
Port 0 is a Member of the Forwarding Group
0B
Port 0 is not a member
Port 0 is a member
1B
Broadcast Port Map andForward Group Port Map
BFGPM
Broadcast Port Map andForward Group Port
Map
Data Sheet
Offset
1AH
108
Reset Value
FFD5H
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
5HV
%3
3
3
3
5HV
3
5HV
3
5HV
3
U
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
BP
14:9
rw
Broadcast Portmap
See Chapter 3.1.20 Packet Forwarding for more detailed information.
P5
8
rw
Port 5 is a Member of the Forwarding Group
0B
Port 5 is not a member
1B
Port 5 is a member
P4
7
rw
Port 4 is a Member of the Forwarding Group
0B
Port 4 is not a member
1B
Port 4 is a member
P3
6
rw
Port 3 is a Member of the Forwarding Group
Port 3 is not a member
0B
1B
Port 3 is a member
Res
5
r
Reserved
P2
4
rw
Port 2 is a Member of the Forwarding Group
Port 2 is not a member
0B
1B
Port 2 is a member
Res
3
r
Reserved
P1
2
rw
Port 1 is a Member of the Forwarding Group
Port 1 is not a member
0B
1B
Port 1 is a member
Res
1
r
Reserved
P0
0
rw
Port 0 is a Member of the Forwarding Group
Port 0 is not a member
0B
1B
Port 0 is a member
Multicast Port Map and Forward Group Port Map
MFGPM
Multicast Port Map and Forward Group Port
Map
Offset
1BH
Reset Value
FFD5H
5HV
03
3
3
3
5HV
3
5HV
3
5HV
3
U
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Data Sheet
109
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
Res
15
r
Reserved
MP
14:9
rw
Multicast Portmap
See Chapter 3.1.20 Packet Forwarding for more detailed information.
P5
8
rw
Port 5 is a member of the Forwarding Group
Port 5 is not a member
0B
1B
Port 5 is a member
P4
7
rw
Port 4 is a member of the Forwarding Group
Port 4 is not a member
0B
1B
Port 4 is a member
P3
6
rw
Port 3 is a member of the Forwarding Group
Port 3 is not a member
0B
1B
Port 3 is a member
Res
5
r
Reserved
P2
4
rw
Port 2 is a member of the Forwarding Group
Port 2 is not a member
0B
1B
Port 2 is a member
Res
3
r
Reserved
P1
2
rw
Port 1 is a member of the Forwarding Group
Port 1 is not a member
0B
1B
Port 1 is a member
Res
1
r
Reserved
P0
0
rw
Port 0 is a member of the Forwarding Group
Port 0 is not a member
0B
1B
Port 0 is a member
Reserve Port Map and Forward Group Port Map
RFGPM
Reserve Port Map and Forward Group Port
Map
Offset
1CH
Reset Value
FFD5H
5HV
53
3
3
3
5HV
3
5HV
3
5HV
3
U
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
RP
14:9
rw
Reserve Portmap
See Chapter 3.1.20 Packet Forwarding for more detailed information.
Data Sheet
110
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
P5
8
rw
Port 5 is a member of the Forwarding Group
Port 5 is not a member
0B
Port 5 is a member
1B
P4
7
rw
Port 4 is a member of the Forwarding Group
0B
Port 4 is not a member
Port 4 is a member
1B
P3
6
rw
Port 3 is a member of the Forwarding Group
0B
Port 3 is not a member
1B
Port 3 is a member
Res
5
r
Reserved
P2
4
rw
Port 2 is a member of the Forwarding Group
Port 2 is not a member
0B
1B
Port 2 is a member
Res
3
r
Reserved
P1
2
rw
Port 1 is a member of the Forwarding Group
Port 1 is not a member
0B
1B
Port 1 is a member
Res
1
r
Reserved
P0
0
rw
Port 0 is a member of the Forwarding Group
Port 0 is not a member
0B
Port 0 is a member
1B
Packet Identification Option, Forward Group Port Map
PIOFGPM
Packet Identification Option, Forward Group
Port Map
063+ ',96
UZ
UZ
Offset
1DH
Reset Value
FFD5H
',,
3
',,3
6
',(
',,3
',6
3
3
3
5HV
3
5HV
3
5HV
3
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Field
Bits
Type
Description
MSPH
15
rw
MLD Snooping Protocol Header
Protocol Header is 01H.
0B
1B
Protocol Header is 3AH.
DIVS
14
rw
Do not Identify VLAN after SNAP
Identify
0B
1B
Don’t identify
DII6P
13
rw
Do not Identify IPV6 in PPPOE
Identify
0B
1B
Don’t identify
Data Sheet
111
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
DIIPS
12
rw
Do not Identify IP in PPPOE after SNAP
0B
Identify
Don’t identify
1B
DIE
11
rw
Do not Identify Ether-Type = 0x0800, IP VER = 6 as IPV6 packets
0B
Identify
Don’t identify
1B
DIIP
10
rw
Do not Identify IP in PPPOE
0B
Identify
1B
Don’t identify
DIS
9
rw
Do not Identify SNAP
Identify
0B
1B
Don’t identify
P5
8
rw
Port 5 is a member of the Forwarding Group
Port 5 is not a member
0B
1B
Port 5 is a member
P4
7
rw
Port 4 is a member of the Forwarding Group
Port 4 is not a member
0B
1B
Port 4 is a member
P3
6
rw
Port 3 is a member of the Forwarding Group
Port 3 is not a member
0B
1B
Port 3 is a member
Res
5
r
Reserved
P2
4
rw
Port 2 is a member of the Forwarding Group
Port 2 is not a member
0B
1B
Port 2 is a member
Res
3
r
Reserved
P1
2
rw
Port 1 is a member of the Forwarding Group
Port 1 is not a member
0B
Port 1 is a member
1B
Res
1
r
Reserved
P0
0
rw
Port 0 is a member of the Forwarding Group
Port 0 is not a member
0B
1B
Port 0 is a member
VLAN Priority Enable and Forward Group Port Map
VPEFGPM
VLAN Priority Enable and Forward Group
Port Map
Offset
1EH
Reset Value
FFD5H
5HV
93(
3
3
3
5HV
3
5HV
3
5HV
3
U
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Data Sheet
112
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
Res
15
r
Reserved
VPE
14:9
rw
VLAN Priority Enable
Do not care the PRI in the tag header
0B
1B
PRI in the tag header will be taken into priority determination
consideration
P5
8
rw
Port 5 is a member of the Forwarding Group
Port 5 is not a member
0B
1B
Port 5 is a member
P4
7
rw
Port 4 is a member of the Forwarding Group
Port 4 is not a member
0B
1B
Port 4 is a member
P3
6
rw
Port 3 is a member of the Forwarding Group
0B
Port 3 is not a member
Port 3 is a member
1B
Res
5
r
Reserved
P2
4
rw
Port 2 is a member of the Forwarding Group
Port 2 is not a member
0B
1B
Port 2 is a membe
Res
3
r
Reserved
P1
2
rw
Port 1 is a member of the Forwarding Group
Port 1 is not a member
0B
1B
Port 1 is a member
Res
1
r
Reserved
P0
0
rw
Port 0 is a member of the Forwarding Group
0B
Port 0 is not a member
Port 0 is a member
1B
Service Priority Enable and Forward Group Port Map
SPEFGPM
Service Priority Enable and Forward Group
Port Map
Offset
1FH
Reset Value
FFD5H
5HV
63(
3
3
3
5HV
3
5HV
3
5HV
3
U
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
Data Sheet
113
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
SPE
14:9
rw
Service Priority Enable
0B
Don’t care IPV4 TOS /IPV6 Traffic Class
Care IPV4 TOS/IPV6 Traffic for priority decision
1B
P5
8
rw
Port 5 is a member of the Forwarding Group
0B
Port 5 is not a member
Port 5 is a member
1B
P4
7
rw
Port 4 is a member of the Forwarding Group
0B
Port 4 is not a member
1B
Port 4 is a member
P3
6
rw
Port 3 is a member of the Forwarding Group
Port 3 is not a member
0B
1B
Port 3 is a member
Res
5
r
Reserved
P2
4
rw
Port 2 is a member of the Forwarding Group
Port 2 is not a member
0B
1B
Port 2 is a member
Res
3
r
Reserved
P1
2
rw
Port 1 is a member of the Forwarding Group
Port 1 is not a member
0B
1B
Port 1 is a member
Res
1
r
Reserved
P0
0
rw
Port 0 is a member of the Forwarding Group
Port 0 is not a member
0B
1B
Port 0 is a member
Input Force No Tag and Forward Group Port Map
IFNTFGPM
Input Force No Tag and Forward Group Port
Map
Offset
20H
Reset Value
FFD5H
5HV
,)17(
3
3
3
5HV
3
5HV
3
5HV
3
U
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
IFNTE
14:9
rw
Input Force No TAG Enable
Disabled
0B
1B
Enabled
Data Sheet
114
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
P5
8
rw
Port 5 is a member of the Forwarding Group
Port 5 is not a member
0B
Port 5 is a member
1B
P4
7
rw
Port 4 is a member of the Forwarding Group
0B
Port 4 is not a member
Port 4 is a member
1B
P3
6
rw
Port 3 is a member of the Forwarding Group
0B
Port 3 is not a member
1B
Port 3 is a member
Res
5
r
Reserved
P2
4
rw
Port 2 is a member of the Forwarding Group
Port 2 is not a member
0B
1B
Port 2 is a member
Res
3
r
Reserved
P1
2
rw
Port 1 is a member of the Forwarding Group
Port 1 is not a member
0B
1B
Port 1 is a member
Res
1
r
Reserved
P0
0
rw
Port 0 is a member of the Forwarding Group
Port 0 is not a member
0B
Port 0 is a member
1B
Ingress Filter andForward Group Port Map
IFFGPM
Ingress Filter andForward Group Port Map
Offset
21H
Reset Value
FFD5H
5HV
,)(
3
3
3
5HV
3
5HV
3
5HV
3
U
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
IFE
14:9
rw
Ingress Filter Enable
Doesn’t filter
0B
1B
Filters
P5
8
rw
Port 5 is a member of the Forwarding Group
Port 5 is not a member
0B
1B
Port 5 is a member
P4
7
rw
Port 4 is a member of the Forwarding Group
0B
Port 4 is not a member
Port 4 is a member
1B
Data Sheet
115
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
P3
6
rw
Port 3 is a member of the Forwarding Group
0B
Port 3 is not a member
Port 3 is a member
1B
Res
5
r
Reserved
P2
4
rw
Port 2 is a member of the Forwarding Group
0B
Port 2 is not a member
Port 2 is a member
1B
Res
3
r
Reserved
P1
2
rw
Port 1 is a member of the Forwarding Group
0B
Port 1 is not a member
Port 1 is a member
1B
Res
1
r
Reserved
P0
0
rw
Port 0 is a member of the Forwarding Group
0B
Port 0 is not a member
Port 0 is a member
1B
VLAN Security Disable and Forward Group Port Map
VSDFGPM
VLAN Security Disable and Forward Group
Port Map
Offset
22H
Reset Value
FFD5H
5HV
96'
3
3
3
5HV
3
5HV
3
5HV
3
U
UZ
UZ
UZ
UZ
U
UZ
U
UZ
U
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
VSD
14:9
rw
VLAN Security Disable
0B
Do not disable
Disable
1B
P5
8
rw
Port 5 is a member of the Forwarding Group
0B
Port 5 is not a member
Port 5 is a member
1B
P4
7
rw
Port 4 is a member of the Forwarding Group
0B
Port 4 is not a member
1B
Port 4 is a member
P3
6
rw
Port 3 is a member of the Forwarding Group
Port 3 is not a member
0B
1B
Port 3 is a member
Res
5
r
Reserved
Data Sheet
116
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
P2
4
rw
Port 2 is a member of the Forwarding Group
0B
Port 2 is not a member
Port 2 is a member
1B
Res
3
r
Reserved
P1
2
rw
Port 1 is a member of the Forwarding Group
0B
Port 1 is not a member
Port 1 is a member
1B
Res
1
r
Reserved
P0
0
rw
Port 0 is a member of the Forwarding Group
0B
Port 0 is not a member
Port 0 is a member
1B
Data Sheet
117
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Buffer Threshold Register 0
BT0
Buffer Threshold Register 0
Offset
23H
Reset Value
0000H
5HV
U
Field
Bits
Type
Description
Res
15:0
r
Reserved
Buffer Threshold Register 1
BT1
Buffer Threshold Register 1
Offset
24H
Reset Value
0000H
5HV
U
Field
Bits
Type
Description
Res
15:0
r
Reserved
IGMP/MLDTRAP Enable and Input Jam Threshold Register
IMEIJT
IGMP/MLDTRAP Enable and Input Jam
Threshold Register
Data Sheet
Offset
25H
Reset Value
1000H
4:
,07(
,-7
UZ
UZ
UZ
118
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
Q1W
15:12
rw
Queue 1 Weight
See Chapter 3.1.15 Priority Queue for more detail information.
IMTE
11:6
rw
IGMP/MLD Trap Enable
It is a per port function.
0B
The port does not enable its multicast snooping function. Trap
MLD_IPV6, MLD_IP and IGMP_IP are useless in this port
The port enables its multicast snooping function. Trap MLD_IPV6,
1B
MLD_IP and IGMP_IP are useful in this port
IJT
5:0
rw
Input Jam Threshold
Queue 2 Weight, VID Exist Check, and PPPOE Port Only
Q2WVECPO
Queue 2 Weight, VID Exist Check, and
PPPOE Port Only
Offset
26H
Reset Value
1000H
4:
9&
332
UZ
UZ
UZ
Field
Bits
Type
Description
Q2W
15:12
rw
Queue 2 Weight
See Chapter 3.1.15 Priority Queue for more detail information.
VC
11:6
rw
VID Check
It is a per port function.
Doesn’t check
0B
1B
checks
PPO
5:0
rw
PPPOE Port Only
It’s a per port function
The port is not a PPPOE Only port
0B
The port is a PPPOE Only port
1B
Queue 3 Weight, Back to Port VLAN, and Admit Only VLAN-Tagged
Q3WBPVAO
Queue 3 Weight, Back to Port VLAN, and
Admit Only VLAN-Tagged
Data Sheet
Offset
27H
119
Reset Value
1000H
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
4:
%39
$2973
UZ
UZ
UZ
Field
Bits
Type
Description
Q3W
15:12
rw
Queue 3 Weight
See Chapter 3.1.15 Priority Queue for more detail information.
BPV
11:6
rw
Back To Port VLAN
It is a per port function
0B
Doesn’t back to Port VLAN
Backs to Port VLAN
1B
AOVTP
5:0
rw
Admit Only VLAN_Tagged Packet
It is a per port function
The port doesn’t check if the packets are VLAN-Tagged
0B
1B
The port drops the packets that carry no VID. (That is Untagged
Packets or Priority-Tagged Packets)
Input Double Tag Enable, and P0VID[11:4]
IDTEP
Input Double Tag Enable, and P0VID[11:4]
Offset
28H
Reset Value
0000H
5HV
5HV
39,'BB
UZ
UZ
UZ
Field
Bits
Type
Description
Res
15:14
rw
Reserved
Res
13:8
rw
Reserved
P0VID_11_4
7:0
rw
P0VID[11:4]
VID bit 11 ~ 4 fo Port 0
Output Double Tag Enable, and P1VID[11:4]
ODTEP
Output Double Tag Enable, and P1VID[11:4]
Data Sheet
Offset
29H
120
Reset Value
0000H
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
5HV
5HV
5HV
%&76
%30
39,'BB
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
Res
15:14
rw
Reserved
Res
13:12
rw
Reserved
Res
11
rw
Reserved
BCTS
10:9
rw
Bandwidth Control Timer Select
00B 8 ms, 64Kbps step, apply to 64Kbps~2.2Mbps
01B 1 ms, 512Kbps step, apply to 512Kbps~18Mbps
10B 40 us, 200Kbps step, apply to 200Kbps~100Mbps
11B 500 us, 16Kbps step, apply to 16Kbps~32Mbps
BPM
8
rw
Back Pressure Mechanism
Exit collision state when CRS goes low
0B
1B
Exit collision state when RXDV goes low
P1VID_11_4
7:0
rw
P1VID[11:4]
VID bit 11 ~ 4 of Port 1.
Output Tag Bypass, and P2VID[11:4]
OTBP
Output Tag Bypass, and P2VID[11:4]
Offset
2AH
Reset Value
3F00H
5HV
27%(
39,'BB
UZ
UZ
UZ
Field
Bits
Type
Description
Res
15:14
rw
Reserved
OTBE
13:8
rw
Output Tag Bypass Enable
It’s a per port function. See Chapter 3.1.14.12 Egress Tag Rule for more
detailed information.
P2VID_11_4
7:0
rw
P2VID[11:4]
VID bit 11 ~ 4 of Port 2.
P3VID[11:4], and P4VID[11:4]
Data Sheet
121
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
P11_4
P3VID[11:4], and P4VID[11:4]
Offset
2BH
Reset Value
0000H
39,'BB
39,'BB
UZ
UZ
Field
Bits
Type
Description
P4VID_11_4
15:8
rw
P4VID[11:4]
VID bit 11 ~ 4 of Port 4.
P3VID_11_4
7:0
rw
P3VID[11:4]
VID bit 11 ~ 4 of Port 3.
Reserved Address Control, and P5VID[11:4]
RACP
Reserved Address Control, and P5VID[11:4]
$0$ $0$ $0$ $0$
UZ
UZ
UZ
UZ
Offset
2CH
Reset Value
D000H
7$*B6+,)7
39,'BB
UZ
UZ
Field
Bits
Type
Description
AMA3
15
rw
Action of MAC Address 3
The Action of MAC Address = 0180C2000010H ~ 0180C20000FFH
AMA2
14
rw
Action of MAC Address 2
The Action of MAC Address = 0180C2000002H ~ 0180C200000FH
AMA1
13
rw
Action of MAC Address 1
The Action of MAC Address = 0180C2000001H
AMA0
12
rw
Action of MAC Address 0
The Action of MAC Address = 0180C2000000H
TAG_SHIFT
11:8
rw
Tag Shift
P5VID_11_4
7:0
rw
P5VID[11:4]
VID bit 11 ~ 4 of Port 5
PHY Control Register
Data Sheet
122
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
PHYC
PHY Control Register
&,&' 5HV
UZ
UZ
Offset
2DH
Reset Value
4442H
5HV
5HV
5HV
5HV
5HV
5HV
5HV
5HV
5HV
5HV
5HV
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
CICD
15
rw
Chip ID Check Disable
0B
Checks CHIP ID in 32 bit SDC/SDO
Doesn’t check CHIP ID in 32 bit SDC/SDIO
1B
Res
14
rw
Reserved
Res
13
rw
Reserved
Res
12:11
rw
Reserved
Res
10
rw
Reserved
Res
9
rw
Reserved
Res
8
rw
Reserved
Res
7
rw
Reserved
Res
6
rw
Reserved
Res
5
rw
Reserved
Res
4
rw
Reserved
Res
3:2
rw
Reserved
Res
1:0
rw
Reserved
ADM TAG Ether Type
ATET
ADM TAG Ether Type
Offset
2EH
Reset Value
0000H
$7(7
UZ
Data Sheet
123
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
ATET
15:0
rw
ADM TAG Ether Type
This value is used by the user to define their Ether-Type. When Special
Tag Receive is enabled, Samurai-6M/6MX (ADM6996M/MX) checks the
packets on the CPU port to see if the two bytes following the SA are the
same as ADM TAG Ether Type . If they are different, Samurai-6M/6MX
(ADM6996M/MX) bypasses the Special Tag. If the same, Samurai6M/6MX (ADM6996M/MX) will use the value in the Special Tag to do
switching decisions .
PHY Restart Register
PR
PHY Restart Register
Offset
2FH
Reset Value
0000H
5(67$57
UZ
Field
Bits
Type
Description
RESTART
15:0
rw
Restart
Samurai-6M/6MX (ADM6996M/MX) writes this register to restart all the
PHYs in the switch. The value written is not important.
Miscellaneous Register
MISC
Miscellaneous Register
Offset
30H
5HV
5HV
5HV
3
5HV
5HV
UZ
UZ
UZ
UZ
UZ
UZ
'+&2
/B/
'3
UZ
UZ
Field
Bits
Type
Description
Res
15
rw
Reserved
Res
14
rw
Reserved
Res
13
rw
Reserved
Data Sheet
%
UZ
124
Reset Value
0987H
5HV 0&(% 5HV
UZ
UZ
UZ
5HV
5HV
5HV
5HV
UZ
UZ
UZ
UZ
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
P4
12
rw
Port 4 LED Mode
LinkAct/DupCol/Speed.
0B
Link/Act/Speed.
1B
Res
11
rw
Reserved
Res
10
rw
Reserved
DHCOL_LED_ 9
EN
rw
Dual Speed Hub COL_LED Enable
0B
Normal LED display.
1B
Dual Speed Hub LED display. Port0 Col LED: 10M Col LED. Port1
Col LED: 100M Col LED.
DP
8
rw
Drop Packets
Drop packets when the link partner does not follow the PAUSE protocol.
Disable.
0B
1B
Enable to drop packets.
B
7
rw
BYPASS
Bypass Tag/Untag function.
Disable.
0B
Enable to bypass Tag/Untag function
1B
Res
6
rw
Reserved
MCEB
5
rw
MAC Clone Enable Bits Select
0B
Select 1 bit MAC Clone function.
Select 2 bits MAC Clone function.
1B
Res
4
rw
Reserved
Res
3
rw
Reserved
Res
2
rw
Resreved
Res
1
rw
Reserved
Res
0
rw
Reserved
Basic Bandwidth Control Register 0
BBC0
Basic Bandwidth Control Register 0
Offset
31H
Reset Value
0000H
5%:
B7+
5%:B7+
5%:
B7+
5%:B7+
5%:
B7+
5%:B7+
5%:
B7+
5%:B7+
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
R3BW_TH1
15
rw
Port 3 Receive Bandwidth Maximum[3].
See register 0033H, P3RBCE for more details.
R3BW_TH0
14:12
rw
Port 3 Receive Bandwidth Configuration
See register 0033H, P3RBCE for more details.
Data Sheet
125
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
R2BW_TH1
11
rw
Port 2 Receive Bandwidth Maximum[3].
See register 0033H, P2RBCE for more details.
R2BW_TH0
10:8
rw
Port 2 Receive Bandwidth Configuration
See register 0033H, P2RBCE for more details.
R1BW_TH1
7
rw
Port 1 Receive Bandwidth Maximum[3].
See register 0033H, P1RBCE for more details.
R1BW_TH0
6:4
rw
Port 1 Receive Bandwidth Configuration
See register 0033H, P1RBCE for more details.
R0BW_TH1
3
rw
Port 0 Receive Bandwidth Maximum[3].
See register 0033H, P0RBCE for more details.
R0BW_TH0
2:0
rw
Port 0 Receive Bandwidth Configuration
See register 0033H, P0RBCE for more details.
Basic Bandwidth Control Register 1
BBC1
Basic Bandwidth Control Register 1
Offset
32H
Reset Value
0000H
7%:
B7+
7%:B7+
7%:
B7+
7%:B7+
5%:
B7+
5%:B7+
5%:
B7+
5%:B7+
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
T1BW_TH1
15
rw
Port 1 Transmit Bandwidth Maximum[3].
See register 0033H, P1TBCE for more details.
T1BW_TH0
14:12
rw
Port 1 Transmit Bandwidth Maximum[2:0].
See register 0033H, P1TBCE for more details.
T0BW_TH1
11
rw
Port 0 Transmit Bandwidth Maximum[3].
See register 0033H, P0TBCE for more details.
T0BW_TH0
10:8
rw
Port 0 Transmit Bandwidth Maximum[2:0].
See register 0033H, P0TBCE for more details.
R5BW_TH1
7
rw
Port 5 Receive Bandwidth Maximum[3].
See register 0033H, P5RBCE for more details.
R5BW_TH0
6:4
rw
Port 5 Receive Bandwidth Configuration
See register 0033H, P5RBCE for more details.
R4BW_TH1
3
rw
Port 4 Receive Bandwidth Maximum[3].
See register 0033H, P4RBCE for more details.
R4BW_TH0
2:0
rw
Port 4 Receive Bandwidth Configuration
See register 0033H, P4RBCE for more details.
Data Sheet
126
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Bandwidth Control Enable Register
BCE
Bandwidth Control Enable Register
,3&3 &/&
UZ
UZ
5HV
UZ
Offset
33H
Reset Value
0000H
$1%& 37% 37% 37% 35% 35% 35% 37% 35% 37% 35% 37% 35%
(
&(
&(
&(
&(
&(
&(
&(
&(
&(
&(
&(
&(
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
IPCP
15
rw
Invert P4 Clock in PCS
Disable
0D
1D
Enable
CLC
14
rw
Check the Length of CRS
0D
Enable
Disable
1D
Res
13
rw
Reserved
ANBCE
12
rw
Samurai-6M/6MX (ADM6996M/MX) New Bandwidth Control Enable
0B
Disable
Enable
1B
P5TBCE
11
rw
Port 5 Transmit Bandwidth Control Enable
The transmitted bandwidth is {T5BW_TH3, T5BW_TH2, T5BW_TH1,
T5BW_TH0, 000000B} kbit/s. K = 1000.
0B
Disable
1B
Enable
P4TBCE
10
rw
Port 4 Transmit Bandwidth Control Enable
The transmitted bandwidth is {T4BW_TH3, T4BW_TH2, T4BW_TH1,
T4BW_TH0, 000000B} kbit/s. K = 1000.
0B
Disable
Enable
1B
P3TBCE
9
rw
Port 3 Transmit Bandwidth Control Enable
The transmitted bandwidth is {T3BW_TH3, T3BW_TH2, T3BW_TH1,
T3BW_TH0, 000000B} kbit/s. K = 1000.
0B
Disable
1B
Enable
P5RBCE
8
rw
Port 5 Receive Bandwidth Control Enable
The received bandwidth is {R5BW_TH3, R5BW_TH2, R5BW_TH1,
R5BW_TH0, 000000B} kbit/s. K = 1000.
0B
Disable
Enable
1B
Data Sheet
127
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
P4RBCE
7
rw
Port 4 Receive Bandwidth Control Enable
The received bandwidth is {R4BW_TH3, R4BW_TH2, R4BW_TH1,
R4BW_TH0, 000000B} kbit/s. K = 1000.
0B
Disable
1B
Enable
P3RBCE
6
rw
Port 3 Receive Bandwidth Control Enable
The received bandwidth is {R3BW_TH3, R3BW_TH2, R3BW_TH1,
R3BW_TH0, 000000B} kbit/s. K = 1000.
Disable
0B
1B
Enable
P2TBCE
5
rw
Port 2 Transmit Bandwidth Control Enable
The transmitted bandwidth is {T2BW_TH3, T2BW_TH2, T2BW_TH1,
T2BW_TH0, 000000B} kbit/s. K = 1000.
0B
Disable
1B
Enable
P2RBCE
4
rw
Port 2 Receive Bandwidth Control Enable
The received bandwidth is {R2BW_TH3, R2BW_TH2, R2BW_TH1,
R2BW_TH0, 000000B} kbit/s. K = 1000.
Disable
0B
1B
Enable
P1TBCE
3
rw
Port 1 Transmit Bandwidth Control Enable
The transmitted bandwidth is {T1BW_TH3, T1BW_TH2, T1BW_TH1,
T1BW_TH0, 000000B} kbit/s. K = 1000.
0B
Disable
Enable
1B
P1RBCE
2
rw
Port 1 Receive Bandwidth Control Enable
The received bandwidth is {R1BW_TH3, R1BW_TH2, R1BW_TH1,
R1BW_TH0, 000000B} kbit/s. K = 1000.
Disable
0B
1B
Enable
P0TBCE
1
rw
Port 0 Transmit Bandwidth Control Enable
The transmitted bandwidth is {T0BW_TH3, T0BW_TH2, T0BW_TH1,
T0BW_TH0, 000000B} kbit/s. K = 1000.
0B
Disable
Enable
1B
P0RBCE
0
rw
Port 0 Receive Bandwidth Control Enable
The received bandwidth is {R0BW_TH3, R0BW_TH2, R0BW_TH1,
R0BW_TH0, 000000B} kbit/s. K = 1000.
Disable
0B
1B
Enable
Extended Bandwidth Control Register 0
EBC0
Extended Bandwidth Control Register 0
Data Sheet
Offset
34H
128
Reset Value
0000H
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
7%:
B7+
7%:B7+
7%:
B7+
7%:B7+
7%:
B7+
7%:B7+
7%:
B7+
7%:B7+
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
T5BW_TH1
15
rw
Port 5 Transmit Bandwidth Maximum[3].
See register 0033H, P5TBCE for more details.
T5BW_TH0
14:12
rw
Port 5 Transmit Bandwidth Maximum[2:0].
See register 0033H, P5TBCE for more details.
T4BW_TH1
11
rw
Port 4 Transmit Bandwidth Maximum[3].
See register 0033H, P4TBCE for more details.
T4BW_TH0
10:8
rw
Port 4 Transmit Bandwidth Maximum[2:0].
See register 0033H, P4TBCE for more details.
T3BW_TH1
7
rw
Port 3 Transmit Bandwidth Maximum[3].
See register 0033H, P3TBCE for more details.
T3BW_TH0
6:4
rw
Port 3 Transmit Bandwidth Maximum[2:0].
See register 0033H, P3TBCE for more details.
T2BW_TH1
3
rw
Port 2 Transmit Bandwidth Maximum[3].
See register 0033H, P2TBCE for more details.
T2BW_TH0
2:0
rw
Port 2 Transmit Bandwidth Maximum[2:0].
See register 0033H, P2TBCE for more details.
Extended Bandwidth Control Register 1
EBC1
Extended Bandwidth Control Register 1
Offset
35H
Reset Value
0000H
5%:B7+
5%:B7+
5%:B7+
5%:B7+
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
R3BW_TH2
15:12
rw
Port 3 Receive Bandwidth Maximum[7:4].
See register 0033H, P3RBCE for more details.
R2BW_TH2
11:8
rw
Port 2 Receive Bandwidth Maximum[7:4].
See register 0033H, P2RBCE for more details.
R1BW_TH2
7:4
rw
Port 1 Receive Bandwidth Maximum[7:4].
See register 0033H, P1RBCE for more details.
Data Sheet
129
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
R0BW_TH2
3:0
rw
Port 0 Receive Bandwidth Maximum[7:4].
See register 0033H, P0RBCE for more details.
Extended Bandwidth Control Register 2
EBC2
Extended Bandwidth Control Register 2
Offset
36H
Reset Value
0000H
7%:B7+
7%:B7+
5%:B7+
5%:B7+
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
T1BW_TH2
15:12
rw
Port 1 Transmit Bandwidth Maximum[7:4]
See register 0033H, P1TBCE for more details.
T0BW_TH2
11:8
rw
Port 0 Transmit Bandwidth Maximum[7:4].
See register 0033H, P0TBCE for more details.
R5BW_TH2
7:4
rw
Port 5 Receive Bandwidth Maximum[7:4].
See register 0033H, P5RBCE for more details.
R4BW_TH2
3:0
rw
Port 4 Receive Bandwidth Maximum[7:4].
See register 0033H, P4RBCE for more details.
Data Sheet
130
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Extended Bandwidth Control Register 3
EBC3
Extended Bandwidth Control Register 3
Offset
37H
Reset Value
0000H
7%:B7+
7%:B7+
7%:B7+
7%:B7+
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
T5BW_TH2
15:12
rw
Port 5 Transmit Bandwidth Maximum[7:4].
See register 0033H, P5TBCE for more details.
T4BW_TH2
11:8
rw
Port 4 Transmit Bandwidth Maximum[7:4].
See register 0033H, P4TBCE for more details.
T3BW_TH2
7:4
rw
Port 3 Transmit Bandwidth Maximum[7:4].
See register 0033H, P3TBCE for more details.
T2BW_TH2
3:0
rw
Port 2 Transmit Bandwidth Maximum[7:4].
See register 0033H, P2TBCE for more details.
Extended Bandwidth Control Register 4
EBC4
Extended Bandwidth Control Register 4
Offset
38H
Reset Value
0000H
)0',
;
5%:B7+
5%:B7+
5%:B7+
5%:B7+
5%:B7+
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
FMDIX0
15
rw
Port 0 MDIX Control
This bit can be used for Port 0 MDI/MDIX selection. It is useful when Port
0 Crossover Auto Detect is disabled and 16 bits management interface
(SDC/SDIO) is used.
Using MDI
0B
Using MDIX
1B
R4BW_TH3
14:12
rw
Port 4 Receive Bandwidth Maximum[10:8].
See register 0033H, P4RBCE for more details.
Data Sheet
131
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
R3BW_TH3
11:9
rw
Port 3 Receive Bandwidth Maximum[10:8].
See register 0033H, P3RBCE for more details.
R2BW_TH3
8:6
rw
Port 2 Receive Bandwidth Maximum[10:8].
See register 0033H, P2RBCE for more details.
R1BW_TH3
5:3
rw
Port 1 Receive Bandwidth Maximum[10:8].
See register 0033H, P1RBCE for more details.
R0BW_TH3
2:0
rw
Port 0 Receive Bandwidth Maximum[10:8].
See register 0033H, P0RBCE for more details.
Extended Bandwidth Control Register 5
EBC5
Extended Bandwidth Control Register 5
Offset
39H
Reset Value
0000H
)0',
;
7%:B7+
7%:B7+
7%:B7+
7%:B7+
5%:B7+
U
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
FMDIX1
15
r
Port 1 MDIX Control
This bit can be used for Port 1 MDI/MDIX selection. It is useful when Port
1 Crossover Auto Detect is disabled and 16 bits management interface
(SDC/SDIO) is used.
Using MDI
0B
Using MDIX
1B
T3BW_TH3
14:12
rw
Port 3 Transmit Bandwidth Maximum[10:8].
See register 0033H, P3TBCE for more details.
T2BW_TH3
11:9
rw
Port 2 Transmit Bandwidth Maximum[10:8].
See register 0033H, P2TBCE for more details.
T1BW_TH3
8:6
rw
Port 1 Transmit Bandwidth Maximum[10:8].
See register 0033H, P1TBCE for more details.
T0BW_TH3
5:3
rw
Port 0 Transmit Bandwidth Maximum[10:8].
See register 0033H, P0TBCE for more details.
R5BW_TH3
2:0
rw
Port 5 Receive Bandwidth Maximum[10:8].
See register 0033H, P5RBCE for more details.
Default VLAN Member and Extended Bandwidth Control Register 6
Data Sheet
132
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
DVMEBC6
Default VLAN Member and Extended
Bandwidth Control Register 6
Offset
3AH
Reset Value
0FC0H
5HV
'90
7%:B7+
7%:B7+
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
Res
15:12
rw
Reserved
DVM
11:6
rw
Default VLAN Member
T5BW_TH3
5:3
rw
Port 5 Transmit Bandwidth Maximum[10:8].
See register 0033H, P5TBCE for more details.
T4BW_TH3
2:0
rw
Port 4 Transmit Bandwidth Maximum[10:8].
See register 0033H, P4TBCE for more details.
New Storm Register 0
NS0
New Storm Register 0
Offset
3BH
6725 6725
5HV 0B'
0B(1
U
UZ
Reset Value
0000H
67250BB7+
UZ
UZ
Field
Bits
Type
Description
Res
15
r
Reserved
STORM_DRO 14
P_EN
rw
Storm Drop Enable
0B
Doesn’t drop in the storming period
Drops in the storming period
1B
STORM_EN
rw
Storm Enable
0B
Disable Samurai-6M/6MX (ADM6996M/MX) style broadcast storm
protection
Enable Samurai-6M/6MX (ADM6996M/MX) style broadcast storm
1B
protection
Data Sheet
13
133
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
STORM_100_ 12:0
TH
Data Sheet
Type
Description
rw
100M Threshold
See Chapter 3.1.9 Broadcast Storm for more detailed information. It is
used when all ports link up in the 100M. The upper bound is reached
when the number of the packets received during the 50 ms is over 100M
Threshold.
134
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
New Storm Register 1
NS1
New Storm Register 1
Offset
3CH
)0', )0', )0',
;
;
;
UZ
UZ
Reset Value
0000H
67250BB7+
UZ
UZ
Field
Bits
Type
Description
FMDIX4
15
rw
Port 4 MDIX Control
This bit can be used for Port 4 MDI/MDIX selection. It is useful when Port
4 Crossover Auto Detect is disabled and 16 bits management interface
(SDC/SDIO) is used.
Using MDI
0B
1B
Using MDIX
FMDIX3
14
rw
Port 3 MDIX Control
This bit can be used for Port 3 MDI/MDIX selection. It is useful when Port
3 Crossover Auto Detect is disabled and 16 bits management interface
(SDC/SDIO) is used.
Using MDI
0B
Using MDIX
1B
FMDIX2
13
rw
Port 2 MDIX Control
This bit can be used for Port 2 MDI/MDIX selection. It is useful when Port
2 Crossover Auto Detect is disabled and 16 bits management interface
(SDC/SDIO) is used.
Using MDI
0B
Using MDIX
1B
rw
10M Threshold
See Chapter 3.1.9 Broadcast Storm for more detailed information. It is
used when one of ports link up in the 10M. The upper bound is reached
when the number of the packets received during the 50 ms is over 10M
Threshold.
STORM_10_T 12:0
H
New Reserve Address Control Register 0
NRAC0
New Reserve Address Control Register 0
Data Sheet
Offset
3DH
135
Reset Value
00FDH
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
157%
3*
35,B6
35,B%
UZ
UZ
UZ
UZ
533 533 *33 533 533 333
UZ
UZ
UZ
UZ
UZ
UZ
633
%33
UZ
UZ
Field
Bits
Type
Description
NRTB
15:14
rw
New Reserve TXTAG for BPDU
00B System Default Tag
01B Unmodified
10B Always Tagged
11B Always Untagged
PG
13:12
rw
PRI for GXRP
00B Queue 0
01B Queue 1
10B Queue 2
11B Queue 3
PRI_S
11:10
rw
PRI for SLOW/PAE/RESER_R0/RESER_R1/RESER_R2/RESER_R3
00B Queue 0
01B Queue 1
10B Queue 2
11B Queue 3
PRI_B
9:8
rw
PRI for BPDU
00B Queue 0
01B Queue 1
10B Queue 2
11B Queue 3
R3PP
7
rw
RESER_R3 Pass Portmap
RESER_R3 Pass Portmap is 000000B
0B
1B
RESER_R3 Pass Pormap is 111111B
R2PP
6
rw
RESER_R2 Pass Portmap
0B
RESER_R2 Pass Portmap is 000000B
1B
RESER_R2 Pass Pormap is 111111B
GPP
5
rw
GXRP Pass Portmap
0B
GXRP Pass Portmap is 000000B
1B
GXRP Pass Pormpap is 111111B
R1PP
4
rw
RESER_R1 Pass Portmap
0B
RESER_R1 Pass Portmap is 000000B
1B
RESER_R1 Pass Portmap is 111111B
R0PP
3
rw
RESER_R0 Pass Portmap
0B
RESER_R0 Pass Portmap is 000000B
1B
RESER_R0 Pass Portmap is 111111B
PPP
2
rw
PAE Pass Portmap
PAE Pass Portmap is 000000B
0B
1B
PAE Pass Portpap is 111111B
Data Sheet
136
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
SPP
1
rw
Slow Pass Portmap
0B
SLOW Pass Portmap is 000000B
1B
SLOW Pass Portpap is 111111B
BPP
0
rw
BPDU Pass Portmap
0B
BPDU Pass Portmap is 000000B
1B
BPDU Pass Portpap is 111111B
New Reserve Address Control Register 1
NRAC1
New Reserve Address Control Register 1
0&$
0&$
UZ
UZ
Offset
3EH
Reset Value
0000H
150* 1506 050% 156* 1566 156% 15&* 15&6 15&%
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
157*
1576
UZ
UZ
Field
Bits
Type
Description
MCA1
15
rw
Mac Control Action 1
Mac Control Action when OPCODE is 01H
0B
The same as Mac Control Action when OPCODE is not 01H
1B
Discards
MCA2
14:13
rw
Mac Control Action 2
Mac Control Action whenOPCODE is not 01H
00B Defaults Output Ports
01B Discards
10B If the receiving port is the CPU port, forward it to the default output
ports. If the receiving port is not the CPU port, forward it to the CPU
port
11B Forwards to the default output ports except the CPU port
NRMG
12
rw
New Reserve Management for GXRP
0B
Doesn’t identify as management packets
Identifies as management packets
1B
NRMS
11
rw
New Reserve Management for
SLOW/PAE/RESER_R0/RESER_R1/RESER_R2/RESER_R3
Doesn’t identify as management packets
0B
1B
Identifies as management packets
MRMB
10
rw
New Reserve Management for BPDU
0B
Doesn’t identify as management packets
Identifies as management packets
1B
NRSG
9
rw
New Reserve Span.for GXRP
0B
Doesn’t identify as management packets
Identifies as management packets
1B
Data Sheet
137
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
NRSS
8
rw
New Reserve Span for
SLOW/PAE/RESER_R0/RESER_R1/RESER_R2/RESER_R3
Doesn’t identify as span packets
0B
1B
Identifies as span packets
NRSB
7
rw
New Reserve SPAN for BPDU
Doesn’t identify as span packets
0B
1B
Identifies as span packets
NRCG
6
rw
New Reserve Cross_VLAN for GXRP
0B
Follows VLAN
Crosses VLAN
1B
NRCS
5
rw
New Reserve Cross_VLAN. for
SLOW/PAE/RESER_R0/RESER_R1/RESER_R2/RESER_R3
Follows VLAN
0B
1B
Crosses VLAN
NRCB
4
rw
New Reserve Cross_VLAN for BPDU
0B
Follows VLAN
Crosses VLAN
1B
NRTG
3:2
rw
New Reserve TXTAG for GXRP
00B System Default Tag
01B Unmodified
10B Always Tagged
11B Always Untagged
NRTS
1:0
rw
New Reserve TXTAG for
SLOW/PAE/RESER_R0/RESER_R1/RESER_R2/RESER_R3
00B System Default Tag
01B Unmodified
10B Always Tagged
11B Always Untagged
Hardware IGMP Control Register
HIC
Hardware IGMP Control Register
Data Sheet
Offset
3FH
Reset Value
7C80H
4,
59
'53
UZ
UZ
UZ
138
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
QI
15:8
rw
Query Interval
The register is used to define Query_Interval when hardware based
IGMP snooping function is enabled (000CH, HISE). The automatically
learned router port will be aged out if no IGMP Query frame received from
the router port for (Query_Interval * Robust Variable) seconds.
RV
7:6
rw
Robust Variable
The register is used to define Robust_Variable when hardware based
IGMP snooping function is enabled (000CH, HISE).
00B Reserved
01B 1 time
10B 2 times
11B 3 times
DRP
5:0
rw
Default Router Portmap
The register is used to define Static Router Port when hardware based
IGMP snooping function and default router port function are enabled
(000CH, HISE & HIDRE).
4.2
EEPROM Extended Registers
VLAN Filter 0 Low
VF0L
VLAN Filter 0 Low
Offset
40H
Reset Value
003FH
),'
70
0
UZ
UZ
UZ
Field
Bits
Type
Description
FID
15:12
rw
FID
The forwarding or learning group that the VID is assigned.
TM
11:6
rw
Tagged Member
These bits indicate which ports are associated with the VID should
transmit tagged packets.Tagged Member[x] Description.
Port x should transmit untagged packets
0B
1B
Port x should transmit tagged packets
Data Sheet
139
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
M
5:0
rw
Member
These bits indicate which ports are the members of the VLAN.Member[x]
Description.
Port x is not a VLAN member
0B
1B
Port x is a VLAN member
Similar Registers
Table 58
VFxL Registers
Register Short Name
Register Long Name
Offset Address
VF1L
VLAN Filter 1 Low
42H
VF2L
VLAN Filter 2 Low
44H
VF3L
VLAN Filter 3Low
46H
VF4L
VLAN Filter 4 Low
48H
VF5L
VLAN Filter 5 Low
4AH
VF6L
VLAN Filter 6 Low
4CH
VF7L
VLAN Filter 7 Low
4EH
VF8L
VLAN Filter 8 Low
50H
VF9L
VLAN Filter 9 Low
52H
VF10L
VLAN Filter 10 Low
54H
VF11L
VLAN Filter 11 Low
56H
VF12L
VLAN Filter 12 Low
58H
VF13L
VLAN Filter 13 Low
5AH
VF14L
VLAN Filter 14 Low
5CH
VF15L
VLAN Filter 15 Low
5EH
Page Number
VLAN Filter 0 High
VF0H
VLAN Filter 0 High
Offset
41H
Reset Value
8001H
99
93
9,'
UZ
UZ
UZ
Field
Bits
Type
Description
VV
15
rw
VLAN_Valid
0B
VLAN filter is not valid
VLAN Filter is valid
1B
Data Sheet
140
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
VP
14:12
rw
VLAN PRI
It indicates the VLAN priority that is associated with VID.
VID
11:0
rw
VID
It indicates the VLAN ID that is associated with FID, Tagged Member,
Member and VLAN PRI.
Similar Registers
All VFxH registers have the same structure and characteristics, see VF0H.
The offset addresses of the other VFxH registers are listed in Table 59.
Table 59
VFxH Registers
Register Short Name
Register Long Name
Offset Address
VF1H
VLAN Filter 1 High
43H
VF2H
VLAN Filter 2 High
45H
VF3H
VLAN Filter 3 High
47H
VF4H
VLAN Filter 4 High
49H
VF5H
VLAN Filter 5 High
4BH
VF6H
VLAN Filter 6 High
4DH
VF7H
VLAN Filter 7 High
4FH
VF8H
VLAN Filter 8 High
51H
VF9H
VLAN Filter 9 High
53H
VF10H
VLAN Filter 10 High
55H
VF11H
VLAN Filter 11 High
57H
VF12H
VLAN Filter 12 High
59H
VF13H
VLAN Filter 13 High
5BH
VF14H
VLAN Filter 14 High
5DH
VF15H
VLAN Filter 15 High
5FH
Page Number
Type Filter 0
TF0
Type Filter 0
Offset
60H
Reset Value
0000H
9&(7
UZ
Field
Bits
Type
Description
VCET
15:0
rw
Value Compared with Ether-Type
Data Sheet
141
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Similar Registers
All TFx registers have the same structure and characteristics, see TF0.
The offset addresses of the other TFx registers are listed in Table 60.
Table 60
TFx Registers
Register Short Name
Register Long Name
Offset Address
TF1
Type Filter 1
61H
TF2
Type Filter 2
62H
TF3
Type Filter 3
63H
TF4
Type Filter 4
64H
TF5
Type Filter 5
65H
TF6
Type Filter 6
66H
TF7
Type Filter 7
67H
Data Sheet
142
Page Number
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Protocol Filter 1 and 0
PF_1_0
Protocol Filter 1 and 0
Offset
68H
Reset Value
0000H
3)5
3)5
UZ
UZ
Field
Bits
Type
Description
PFR1
15:8
rw
Value Compared with Protocol in IP Header
(Protocol Filter 1, 3, 5, 7)
PFR0
7:0
rw
Value Compared with Protocol in IP Header
(Protocol Filter 0, 2, 4, 6)
Similar Registers
All PFx registers have the same structure and characteristics, see PF_1_0.
The offset addresses of the other PFx registers are listed in Table 61.
Table 61
PFx Registers
Register Short Name
Register Long Name
Offset Address
PF_3_2
Protocol Filter 3 and 2
68H
PF_5_4
Protocol Filter 5 and 4
69H
PF_7_6
Protocol Filter 7 and 6
6AH
Page Number
Service Priority Mapping 0
SPM0
Service Priority Mapping 0
Offset
6CH
Reset Value
0000H
34
34
34
34
34
34
34
34
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PQ7
15:14
rw
Priority Queue 7
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 000111B.
Data Sheet
143
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
PQ6
13:12
rw
Priority Queue 6
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 000110B.
PQ5
11:10
rw
Priority Queue 5
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 000101B.
PQ4
9:8
rw
Priority Queue 4
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 000100B.
PQ3
7:6
rw
Priority Queue 3
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 000011B.
PQ2
5:4
rw
Priority Queue 2
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 000010B.
PQ1
3:2
rw
Priority Queue 1
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 000001B.
PQ0
1:0
rw
Priority Queue 0
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 000000B.
00B Queue 0
01B Queue 1
10B Queue 2
11B Queue 3
Service Priority Mapping 1
SPM1
Service Priority Mapping 1
Offset
6DH
Reset Value
0000H
34)
34(
34'
34&
34%
34$
34
34
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PQF
15:14
rw
Priority Queue F
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 001111B
PQE
13:12
rw
Priority Queue E
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 001110B
Data Sheet
144
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
PQD
11:10
rw
Priority Queue D
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 001101B
PQC
9:8
rw
Priority Queue C
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 001100B
PQB
7:6
rw
Priority Queue B
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 001011B
PQA
5:4
rw
Priority Queue A
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 001010B
PQ9
3:2
rw
Priority Queue 9
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 001001B
PQ8
1:0
rw
Priority Queue 8
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 001000B
Service Priority Mapping 2
SPM2
Service Priority Mapping 2
Offset
6EH
Reset Value
0000H
34
34
34
34
34
34
34
34
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PQ17
15:14
rw
Priority Queue 17
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 010111B
PQ16
13:12
rw
Priority Queue 16
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 010110B
PQ15
11:10
rw
Priority Queue 15
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 010101B
PQ14
9:8
rw
Priority Queue 14
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 010100B
Data Sheet
145
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
PQ13
7:6
rw
Priority Queue 13
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 010011B
PQ12
5:4
rw
Priority Queue 12
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 010010B
PQ11
3:2
rw
Priority Queue 11
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 010001B
PQ10
1:0
rw
Priority Queue 10
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 010000B
Service Priority Mapping 3
SPM3
Service Priority Mapping 3
Offset
6FH
Reset Value
0000H
34)
34(
34'
34&
34%
34$
34
34
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PQ1F
15:14
rw
Priority Queue 1F
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 011111B
PQ1E
13:12
rw
Priority Queue 1E
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 011110B
PQ1D
11:10
rw
Priority Queue 1D
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 011101B
PQ1C
9:8
rw
Priority Queue 1C
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 011100B
PQ1B
7:6
rw
Priority Queue 1B
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 011011B
PQ1A
5:4
rw
Priority Queue 1A
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 011010B
Data Sheet
146
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
PQ19
3:2
rw
Priority Queue 19
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 011001B
PQ18
1:0
rw
Priority Queue 18
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 011000B
Service Priority Mapping 4
SPM4
Service Priority Mapping 4
Offset
70H
Reset Value
0000H
34
34
34
34
34
34
34
34
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PQ27
15:14
rw
Priority Queue 27
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 100111B
PQ26
13:12
rw
Priority Queue 26
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 100110B
PQ25
11:10
rw
Priority Queue 25
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 100101B
PQ24
9:8
rw
Priority Queue 24
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 100100B
PQ23
7:6
rw
Priority Queue 23
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 100011B
PQ22
5:4
rw
Priority Queue 22
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 100010B
PQ21
3:2
rw
Priority Queue 21
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 100001B
PQ20
1:0
rw
Priority Queue 20
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 100000B
Data Sheet
147
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Service Priority Mapping 5
SPM5
Service Priority Mapping 5
Offset
71H
Reset Value
0000H
34)
34(
34'
34&
34%
34$
34
34
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PQ2F
15:14
rw
Priority Queue 2F
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 101111B
PQ2E
13:12
rw
Priority Queue 2E
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 101110B
PQ2D
11:10
rw
Priority Queue 2D
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 101101B
PQ2C
9:8
rw
Priority Queue 2C
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 101100B
PQ2B
7:6
rw
Priority Queue 2B
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 101011B
PQ2A
5:4
rw
Priority Queue 2A
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 101010B
PQ29
3:2
rw
Priority Queue 29
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 101001B
PQ28
1:0
rw
Priority Queue 28
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 101000B
Service Priority Mapping 6
SPM6
Service Priority Mapping 6
Data Sheet
Offset
72H
148
Reset Value
0000H
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
34
34
34
34
34
34
34
34
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PQ37
15:14
rw
Priority Queue 37
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 110111B
PQ36
13:12
rw
Priority Queue 36
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 110110B
PQ35
11:10
rw
Priority Queue 35
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 110101B
PQ34
9:8
rw
Priority Queue 34
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 110100B
PQ33
7:6
rw
Priority Queue 33
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 110011B
PQ32
5:4
rw
Priority Queue 32
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 110010B
PQ31
3:2
rw
Priority Queue 31
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 110001B
PQ30
1:0
rw
Priority Queue 30
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 110000B
Service Priority Mapping 7
SPM7
Service Priority Mapping 7
Offset
73H
Reset Value
0000H
34)
34(
34'
34&
34%
34$
34
34
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Data Sheet
149
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
PQ3F
15:14
rw
Priority Queue 3F
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 111111B
PQ3E
13:12
rw
Priority Queue 3E
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 111110B
PQ3D
11:10
rw
Priority Queue 3D
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 111101B
PQ3C
9:8
rw
Priority Queue 3C
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 111100B
PQ3B
7:6
rw
Priority Queue 3B
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 111011B
PQ3A
5:4
rw
Priority Queue 3A
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 111010B
PQ39
3:2
rw
Priority Queue 39
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 111001B
PQ38
1:0
rw
Priority Queue 38
The value in this field is used as the priority queue when the significant 6
bits in the IPV4 TOS/IPV6 Traffic Class are 111000B
Reserve Action for 0180C2000001~0180C2000000
RA_01_00
Reserve Action for
0180C2000001~0180C2000000
5$ 5$ 5$ 5$
B9$
B63
B0* B&9
UZ
UZ
UZ
Offset
74H
5$B7;
7$*
5$B$&
7
UZ
UZ
UZ
Reset Value
0000H
5$ 5$ 5$ 5$
B9$
B63
B0* B&9
UZ
UZ
Field
Bits
Type
Description
RA01_VALID
15
rw
Valid bit for 0180C2000001
0B
Not Valid
Valid
1B
Data Sheet
150
UZ
UZ
5$B7;
7$*
5$B$&
7
UZ
UZ
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
RA01_SPAN
14
rw
Span bit for 0180C2000001
0B
Doesn’t identify as the span packet
Identifies as the span packet
1B
RA01_MG
13
rw
Management bit for 0180C2000001
0B
Doesn’t identify as the management packet
Identifies as the management packet
1B
RA01_CV
12
rw
Cross_VLAN bit for 0180C2000001
0B
Doesn’t identify as the cross_VLAN packet
1B
Identifies as the cross_VLAN packet
RA01_TXTAG 11:10
rw
TXTAG bit for 0180C2000001
00B System Default Tag
01B Unmodified
10B Always Tagged
11B Always Untagged
RA01_ACT
9:8
rw
Action bit for 0180C2000001
00B Portmap is 111111B
01B Portmap is 000000B
10B Portmap is the CPU port if the incoming port is not the CPU port.
But if the incoming port is the CPU port, then Reserve Portmap
contains all the ports, excluding the CPU port
11B Portmap contains all the ports, excluding the CPU port
RA00_VALID
7
rw
Valid bit for 0180C2000000
Not Valid
0B
1B
Valid
RA00_SPAN
6
rw
Span bit for 0180C2000000
Doesn’t identify as the span packet
0B
Identifies as the span packet
1B
RA00_MG
5
rw
Management bit for 0180C2000000
0B
Doesn’t identify as the management packet
Identifies as the management packet
1B
RA00_CV
4
rw
Cross_VLAN bit for 0180C2000000
0B
Doesn’t identify as the cross_VLAN packet
Identifies as the cross_VLAN packet
1B
RA00_TXTAG 3:2
rw
TXTAG bit for 0180C2000000
00B System Default Tag
01B Unmodified
10B Always Tagged
11B Always Untagged
RA00_ACT
rw
Action bit for 0180C2000000
00B Portmap is 111111B
01B Portmap is 000000B
10B Portmap is the CPU port if the incoming port is not the CPU port.
But if the incoming port is the CPU port, then Reserve Portmap
contains all the ports, excluding the CPU port
11B Portmap contains all the ports, excluding the CPU port
Data Sheet
1:0
151
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Similar Registers
All RAx registers have the same structure and characteristics, see RA_01_00.
The offset addresses of the other RAx registers are listed in Table 62.
Table 62
RAx Registers
Register Short Name
Register Long Name
Offset Address
RA_03_02
Reserve Action for
0180C2000003~0180C2000002
75H
RA_05_04
Reserve Action for
0180C2000005~0180C2000004
76H
RA_07_06
Reserve Action for
0180C2000007~0180C2000006
77H
RA_09_08
Reserve Action for
0180C2000009~0180C2000008
78H
RA_0B_0A
Reserve Action for
0180C200000B~0180C200000A
79H
RA_0D_0C
Reserve Action for
0180C200000D~0180C200000C
7AH
RA_0F_0E
Reserve Action for
0180C200000F~0180C200000E
7BH
RA_11_10
Reserve Action for
0180C2000011~0180C2000010
7CH
RA_13_12
Reserve Action for
0180C2000013~0180C2000012
7DH
RA_15_14
Reserve Action for
0180C2000015~0180C2000014
7EH
RA_17_16
Reserve Action for
0180C2000017~0180C2000016
7FH
RA_19_18
Reserve Action for
0180C2000019~0180C2000018
80H
RA_1B_1A
Reserve Action for
0180C200001B~0180C200001A
81H
RA_1D_1C
Reserve Action for
0180C200001D~0180C200001C
82H
RA_1F_1E
Reserve Action for
0180C200001F~0180C200001E
83H
RA_21_20
Reserve Action for
0180C2000021~0180C2000020
84H
RA_23_22
Reserve Action for
0180C2000023~0180C2000022
85H
RA_25_24
Reserve Action for
0180C2000025~0180C2000024
86H
RA_27_26
Reserve Action for
0180C2000027~0180C2000026
87H
RA_29_28
Reserve Action for
0180C2000029~0180C2000028
88H
Data Sheet
152
Page Number
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Table 62
RAx Registers (cont’d)
Register Short Name
Register Long Name
Offset Address
RA_2B_2A
Reserve Action for
0180C200002B~0180C200002A
89H
RA_2D_2C
Reserve Action for
0180C200002D~0180C200002C
8AH
RA_2F_2E
Reserve Action for
0180C200002F~0180C200002E
8BH
Page Number
TCP/UDP Filter 0
TUF0
TCP/UDP Filter 0
Offset
8CH
Reset Value
0000H
9$/B&203
UZ
Field
Bits
Type
Description
VAL_COMP
15:0
rw
Value Compared with the Destination Port Number in the TCP/UDP
Header
Similar Registers
All TUFx registers have the same structure and characteristics, see TUF0.
The offset addresses of the other TUFx registers are listed in Table 65.
Table 63
TUFx Registers
Register Short Name
Register Long Name
Offset Address
TUF1
TCP/UDP Filter 1
8DH
TUF2
TCP/UDP Filter 2
8EH
TUF3
TCP/UDP Filter 3
8FH
TUF4
TCP/UDP Filter 4
90H
TUF5
TCP/UDP Filter 5
91H
TUF6
TCP/UDP Filter 6
92H
TUF7
TCP/UDP Filter 7
93H
Page Number
Type Filter Action
TFA
Type Filter Action
Data Sheet
Offset
94H
153
Reset Value
0000H
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
$7)
$7)
$7)
$7)
$7)
$7)
$7)
$7)
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
ATF7
15:14
rw
Action for Type Filter 7
See register 0094H, ATF0 for more details.
ATF6
13:12
rw
Action for Type Filter 6
See register 0094H, ATF0 for more details.
ATF5
11:10
rw
Action for Type Filter 5
See register 0094H, ATF0 for more details.
ATF4
9:8
rw
Action for Type Filter 4
See register 0094H, ATF0 for more details.
ATF3
7:6
rw
Action for Type Filter 3
See register 0094H, ATF0 for more details.
ATF2
5:4
rw
Action for Type Filter 2
See register 0094H, ATF0 for more details.
ATF1
3:2
rw
Action for Type Filter 1
See register 0094H, ATF0 for more details.
ATF0
1:0
rw
Action for Type Filter 0
00B Type Portmap is Default Output Ports
01B Type Portmap is 000000B
10B Type Portmap is the CPU port if the incoming port is not the CPU
port. But if the incoming port is the CPU port, then Type Portmap
contains Default Output Ports , excluding the CPU port
11B Type Portmap contains Default Output Port, excluding the CPU
port
Protocol Filter Action
PFA
Protocol Filter Action
Offset
95H
Reset Value
0000H
$3)
$3)
$3)
$3)
$3)
$3)
$3)
$3)
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
APF7
15:14
rw
Action for Protocol Filter 7
See register 0095H, APF0 for more details.
Data Sheet
154
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
APF6
13:12
rw
Action for Protocol Filter 6
See register 0095H, APF0 for more details.
APF5
11:10
rw
Action for Protocol Filter 5
See register 0095H, APF0 for more details.
APF4
9:8
rw
Action for Protocol Filter 4
See register 0095H, APF0 for more details.
APF3
7:6
rw
Action for Protocol Filter 3
See register 0095H, APF0 for more details.
APF2
5:4
rw
Action for Protocol Filter 2
See register 0095H, APF0 for more details.
APF1
3:2
rw
Action for Protocol Filter 1
See register 0095H, APF0 for more details.
APF0
1:0
rw
Action for Protocol Filter 0
00B Protocol Portmap is Default Output Ports
01B Protocol Portmap is 000000B
10B Protocol Portmap is the CPU port if the incoming port is not the
CPU port. But if the incoming port is the CPU port, then Type
Portmap contains Default Output Ports, excluding the CPU port
11B Protocol Portmap contains Default Output Ports, excluding the
CPU port
TCP/UDP Action 0
TUA0
TCP/UDP Action 0
Offset
96H
Reset Value
0000H
$78)
783)
$78)
783)
$78)
783)
$78)
783)
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
ATUF3
15:14
rw
Action for TCP/UDP Filter 3.
See register 0096H, ATUF0 for more details.
TUPF3
13:12
rw
TCP/UDP PRI for TCP/UDP Filter 3
See register 0096H, TUPF0 for more details.
ATUF2
11:10
rw
Action for TCP/UDP Filter 2
See register 0096H, ATUF0 for more details.
TUPF2
9:8
rw
TCP/UDP PRI for TCP/UDP Filter 2
See register 0096H, TUPF0 for more details.
ATUF1
7:6
rw
Action for TCP/UDP Filter 1
See register 0096H, ATUF0 for more details.
Data Sheet
155
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
TUPF1
5:4
rw
TCP/UDP PRI for TCP/UDP Filter 1
See register 0096H, TUPF0 for more details.
ATUF0
3:2
rw
Action for TCP/UDP Filter 0
00B Protocol Portmap is Default Output Ports
01B Protocol Portmap is 000000B
10B Protocol Portmap is the CPU port if the incoming port is not the
CPU port. But if the incoming port is the CPU port, then Type
Portmap contains Default Output Ports, excluding the CPU port
11B Protocol Portmap contains Default Output Ports, excluding the
CPU port
TUPF0
1:0
rw
TCP/UDP PRI for TCP/UDP Filter 0
00B Queue 0
01B Queue 1
10B Queue 2
11B Queue 3
TCP/UDP Action 1
TUA1
TCP/UDP Action 1
Offset
97H
Reset Value
0000H
$78)
783)
$78)
783)
$78)
783)
$78)
783)
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
ATUF7
15:14
rw
Action for TCP/UDP Filter 7
See register 0096H, ATUF0 for more details.
TUPF7
13:12
rw
TCP/UDP PRI for TCP/UDP Filter 7
See register 0096H, TUPF0 for more details.
ATUF6
11:10
rw
Action for TCP/UDP Filter 6
See register 0096H, ATUF0 for more details.
TUPF6
9:8
rw
TCP/UDP PRI for TCP/UDP Filter 6
See register 0096H, TUPF0 for more details.
ATUF5
7:6
rw
Action for TCP/UDP Filter 5
See register 0096H, ATUF0 for more details.
TUPF5
5:4
rw
TCP/UDP PRI for TCP/UDP Filter 5
See register 0096H, TUPF0 for more details.
ATUF4
3:2
rw
Action for TCP/UDP Filter 4
See register 0096H, ATUF0 for more details.
TUPF4
1:0
rw
TCP/UDP PRI for TCP/UDP Filter 4
See register 0096H, TUPF0 for more details.
Data Sheet
156
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
TCP/UDP Action 2
TUA2
TCP/UDP Action 2
Offset
98H
Reset Value
0000H
5HV
&203
3,
3,
3,
3,
3,
3,
37
37
37
37
37
37
U
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
Res
15:14
r
Reserved
COMP
13:12
rw
Compare TCP/UDP Source Port or Destination Port
00B Doesn’t Compare
01B Compares Destination Port
10B Compares Source Port
11B Compares Destination Port or Source Port
P5I
11
rw
Port 5 IP over TCP/UDP
0B
Uses TCP/UDP field when packets contain both TCP/UDP and IP
Uses IP field when packets contain both TCP/UDP and IP
1B
P4I
10
rw
Port 4 IP over TCP/UDP
0B
Uses TCP/UDP field when packets contain both TCP/UDP and IP
1B
Uses IP field when packets contain both TCP/UDP and IP
P3I
9
rw
Port 3 IP over TCP/UDP
Uses TCP/UDP field when packets contain both TCP/UDP and IP
0B
1B
Uses IP field when packets contain both TCP/UDP and IP
P2I
8
rw
Port 2 IP over TCP/UDP
Uses TCP/UDP field when packets contain both TCP/UDP and IP
0B
1B
Uses IP field when packets contain both TCP/UDP and IP
P1I
7
rw
Port 1 IP over TCP/UDP
Uses TCP/UDP field when packets contain both TCP/UDP and IP
0B
1B
Uses IP field when packets contain both TCP/UDP and IP
P0I
6
rw
Port 0 IP over TCP/UDP
0B
Uses TCP/UDP field when packets contain both TCP/UDP and IP
Uses IP field when packets contain both TCP/UDP and IP
1B
P5T
5
rw
Port 5 TCP/UDP PRIEN
0B
Doesn’t use TCP/UDP priority
Uses TCP/UDP priority
1B
P4T
4
rw
Port 4 TCP/UDP PRIEN
0B
Doesn’t use TCP/UDP priority
1B
Uses TCP/UDP priority
P3T
3
rw
Port 3 TCP/UDP PRIEN
Doesn’t use TCP/UDP priority
0B
1B
Uses TCP/UDP priority
Data Sheet
157
Revision 1.4, 2006-03-24
Samurai-6M/MX
ADM6996M/MX
Registers Description
Field
Bits
Type
Description
P2T
2
rw
Port 2 TCP/UDP PRIEN
Doesn’t use TCP/UDP priority
0B
Uses TCP/UDP priority
1B
P1T
1
rw
Port 1 TCP/UDP PRIEN
0B
Doesn’t use TCP/UDP priority
Uses TCP/UDP priority
1B
P0T
0
rw
Port 0 TCP/UDP PRIEN
0B
Doesn’t use TCP/UDP priority
1B
Uses TCP/UDP priority
Extended IGMP Control/Special Tag Insert Control
EICSTIC
Extended IGMP Control/Special Tag Insert
Control
Offset
99H
5HV
,$&
UZ
UZ
Field
Bits
Res
IAC
Reset Value
01FFH
,16B ,16B ,16B ,16B ,16B ,16B ,16B ,16B ,16B
,3
5(6 $53 612
7
工商网监
湘ICP备2023018690号
